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5962-9850901NTC PDF预览

5962-9850901NTC

更新时间: 2024-11-07 14:47:43
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑
页数 文件大小 规格书
19页 543K
描述
Field Programmable Gate Array, PQFP240, PLASTIC, QFP-240

5962-9850901NTC 技术参数

生命周期:Active零件包装代码:QFP
包装说明:FQFP,针数:240
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.63
JESD-30 代码:S-PQFP-G240JESD-609代码:e4
长度:32 mm端子数量:240
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class N座面最大高度:4.1 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
端子面层:GOLD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:32 mmBase Number Matches:1

5962-9850901NTC 数据手册

 浏览型号5962-9850901NTC的Datasheet PDF文件第2页浏览型号5962-9850901NTC的Datasheet PDF文件第3页浏览型号5962-9850901NTC的Datasheet PDF文件第4页浏览型号5962-9850901NTC的Datasheet PDF文件第5页浏览型号5962-9850901NTC的Datasheet PDF文件第6页浏览型号5962-9850901NTC的Datasheet PDF文件第7页 
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QPRO™ XQ4000XL Series QML  
High-Reliability FPGAs  
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DS029 (v1.2) February 9, 2000  
Highest Capacity — Over 130,000 Usable Gates  
Additional Routing Over XQ4000E  
XQ4000X Series Features  
Certified to MIL-PRF-38535 Appendix A QML (Qualified  
Manufacturer Listing)  
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almost twice the routing capacity for high-density  
designs  
Ceramic and plastic packages  
Also available under the following standard microcircuit  
drawings (SMD)  
Buffered Interconnect for Maximum Speed  
New Latch Capability in Configurable Logic Blocks  
Improved VersaRing™ I/O Interconnect for Better Fixed  
Pinout Flexibility  
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XQ4013XL 5962-98513  
XQ4036XL 5962-98510  
XQ4062XL 5962-98511  
XQ4085XL 5962-99575  
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Virtually unlimited number of clock signals  
Optional Multiplexer or 2-input Function Generator on  
Device Outputs  
5V tolerant I/Os  
For more information contact the Defense Supply  
Center Columbus (DSCC)  
0.35 µm SRAM process  
http://www.dscc.dla.mis/v/va/smd/smdsrch.html  
Available in -3 speed  
System featured Field-Programmable Gate Arrays  
Introduction  
XQ4000X Series high-performance, high-capacity Field  
Programmable Gate Arrays (FPGAs) provide the benefits  
of custom CMOS VLSI, while avoiding the initial cost, long  
development cycle, and inherent risk of a conventional  
masked gate array.  
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SelectRAM™ memory: on-chip ultra-fast RAM with  
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synchronous write option  
dual-port RAM option  
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Abundant flip-flops  
Flexible function generators  
Dedicated high-speed carry logic  
Wide edge decoders on each edge  
Hierarchy of interconnect lines  
Internal 3-state bus capability  
Eight global low-skew clock or signal distribution  
networks  
The result of thirteen years of FPGA design experience and  
feedback from thousands of customers, these FPGAs com-  
bine architectural versatility, on-chip Select-RAM memory  
with edge-triggered and dual-port modes, increased speed,  
abundant routing resources, and new, sophisticated  
soft-ware to achieve fully automated implementation of  
complex, high-density, high-performance designs.  
System Performance beyond 50 MHz  
Flexible Array Architecture  
Low Power Segmented Routing Architecture  
Systems-Oriented Features  
Refer to the complete Commercial XC4000X Series Field  
Programmable Gate Arrays Data Sheet for more informa-  
tion on device architecture and timing, and the latest Xilinx  
databook for package pinouts other than the CB228  
(included in this data sheet). (Pinouts for XQ4000XL device  
are identical to XC4000XL.)  
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IEEE 1149.1-compatible boundary scan logic  
support  
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Individually programmable output slew rate  
Programmable input pull-up or pull-down resistors  
12 mA Sink Current Per XQ4000XL Output  
Configured by Loading Binary File  
Unlimited reprogrammability  
Readback Capability  
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Program verification  
Internal node observability  
Development System runs on most common computer  
platforms  
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- Interfaces to popular design environments  
- Fully automatic mapping, placement and routing  
- Interactive design editor for design optimization  
DS029 (v1.2) February 9, 2000  
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