Datasheet > 5962-9475001QXA

5962-9475001QXA

更新时间： 2023-05-15 00:00:00

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
29页	416K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28, CERDIP-28

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5962-9475001QXA 数据手册

September 1998

SCANPSC100F

Embedded Boundary Scan Controller

(IEEE 1149.1 Support)

General Description

Features

n Compatible with IEEE Std. 1149.1 (JTAG) Test Access

Port and Boundary Scan Architecture

The SCANPSC100F is designed to interface a generic paral-

lel processor bus to a serial scan test bus. It is useful in im-

proving scan throughput when applying serial vectors to sys-

tem test circuitry and reduces the software overhead that is

associated with applying serial patterns with a parallel pro-

cessor. The ’PSC100F operates by serializing data from the

parallel bus for shifting through the chain of 1149.1 compliant

components (i.e., scan chain). Scan data returning from the

scan chain is placed on the parallel port to be read by the

host processor. Up to two scan chains can be directly con-

trolled with the ’PSC100F via two independent TMS pins.

Scan control is supplied with user specific patterns which

makes the ’PSC100F protocol-independent. Overflow and

underflow conditions are prevented by stopping the test

clock. A 32-bit counter is used to program the number of TCK

cycles required to complete a scan operation within the

boundary scan chain or to complete a ’PSC100F Built-In Self

Test (BIST) operation. SCANPSC100F device drivers and

1149.1 embedded test application code are available with

National’s SCANEase software tools.

n Supported by National’s SCAN Ease (Embedded

Application Software Enabler) Software

n Uses generic, asynchronous processor interface;

compatible with a wide range of processors and PCLK

frequencies

n Directly supports up to two 1149.1 scan chains

n 16-bit Serial Signature Compaction (SSC) at the Test

Data In (TDI) port

n Automatically produces pseudo-random patterns at the

Test Data Out (TDO) port

n Fabricated on FACT 1.5 µm CMOS process

n Supports 1149.1 test clock (TCK) frequencies up to

25 MHz

n TTL-compatible inputs; full-swing CMOS outputs with

24 mA source/sink capability

™

n Standard Microcircuit Drawing (SMD) 5962-9475001

Connection Diagrams

28-Pin DIP and Flatpak

Pin Assignment for LCC

DS100325-18

DS100325-1

™

FACT is a trademark of Fairchild Semiconductor Corporation.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

DS100325

www.national.com

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