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5962-9317501MXA PDF预览

5962-9317501MXA

更新时间: 2024-01-01 08:33:54
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
13页 189K
描述
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

5962-9317501MXA 技术参数

生命周期:ActiveReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.45
系列:ABTJESD-30 代码:R-GDFP-F48
长度:15.875 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):4.6 ns
认证状态:Qualified座面最大高度:3.05 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:9.655 mmBase Number Matches:1

5962-9317501MXA 数据手册

 浏览型号5962-9317501MXA的Datasheet PDF文件第4页浏览型号5962-9317501MXA的Datasheet PDF文件第5页浏览型号5962-9317501MXA的Datasheet PDF文件第6页浏览型号5962-9317501MXA的Datasheet PDF文件第8页浏览型号5962-9317501MXA的Datasheet PDF文件第9页浏览型号5962-9317501MXA的Datasheet PDF文件第10页 
SN54ABT16245A, SN74ABT16245A  
16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS300FMARCH 1994REVISED JULY 2005  
PARAMETER MEASUREMENT INFORMATION  
7 V  
Open  
TEST  
/t  
S1  
S1  
500 Ω  
From Output  
Under Test  
t
Open  
7 V  
PLH PHL  
GND  
t
/t  
PLZ PZL  
C = 50 pF  
(see Note A)  
t
/t  
Open  
L
PHZ PZH  
500 Ω  
3 V  
0 V  
LOAD CIRCUIT  
Timing Input  
Data Input  
1.5 V  
t
w
t
t
h
su  
3 V  
0 V  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
t
t
t
t
t
PHL  
PZL  
PLZ  
PLH  
Output  
Waveform 1  
S1 at 7 V  
3.5 V  
V
V
OH  
1.5 V  
Output  
1.5 V  
1.5 V  
1.5 V  
V
V
+ 0.3 V  
OL  
V
OL  
OL  
(see Note B)  
t
PHL  
PLH  
t
t
PHZ  
PZH  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
V
OH  
− 0.3 V  
OH  
1.5 V  
Output  
1.5 V  
0 V  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
7

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