Datasheet > 5962-9165401MYA

5962-9165401MYA

更新时间： 2024-11-19 07:37:19

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
12页	188K
描述
100K SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CQFP24, CERQUAD-24

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5962-9165401MYA 数据手册

August 1998

100355

Low Power Quad Multiplexer/Latch

puts. A HIGH signal on the Master Reset (MR) input over-

rides all the other inputs and forces the Q outputs LOW. All

inputs have 50 kΩ pulldown resistors.

General Description

The 100355 contains four transparent latches, each of which

can accept and store data from two sources. When both En-

able (E_n) inputs are LOW, the data that appears at an output

is controlled by the Select (S_n) inputs, as shown in the Oper-

ating Mode table. In addition to routing data from either D₀or

D₁, the Select inputs can force the outputs LOW for the case

where the latch is transparent (both Enables are LOW) and

can steer a HIGH signal from either D₀or D₁to an output.

The Select inputs can be tied together for applications re-

quiring only that data be steered from either D₀or D₁. A

positive-going signal on either Enable input latches the out-

Features

n Greater than 40% power reduction of the 100155

n 2000V ESD protection

n Pin/function compatible with 100155

n Voltage compensated operating range −4.2V to −5.7V

n Standard Microcircuit Drawing

(SMD) 5962-9165401

Logic Symbol

DS100294-1

Pin Names

Description

E₁, E₂

S₀, S₁

Enable Inputs (Active LOW)

Select Inputs

Master Reset

_na–D_nd

Data Inputs

Q_a–Q_d

Data Outputs

Complementary Data Outputs

Connection Diagrams

24-Pin DIP

24-Pin Quad Cerpak

DS100294-3

DS100294-2

DS100294

www.national.com

12 3 4 5 6 7...12

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