AD2S80A
DATA TRANSFER
5V
1k⍀
10k⍀
To transfer data the INHIBIT input should be used. The data
will be valid 600 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic “HI”
state to enable the output latches to be updated.
TO COUNTER
(CLOCK)
IN4148
RIPPLE
CLOCK
2N3904
0V
5V
5k⍀
IN4148
BUSY
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO."
Figure 2. Diode Transistor Logic Nand Gate
BUSY Output
DIRECTION Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This corresponds to a change in input rotation
direction but less than 1 LSB.
INHIBIT Input
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
DIGITAL TIMING
V
BUSY
H
t1
RIPPLE
CLOCK
V
L
t2
ENABLE Input
V
H
t3
The ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
t4
V
H
DATA
t5
V
L
INHIBIT
V
H
t6
t7
BYTE SELECT Input
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least signifi-
cant byte will be presented on data output DB9 to DB16 (with
the ENABLE input taken to a logic “LO”) regardless of the
state of the BYTE SELECT pin. Note that when the AD2S80A is
used with a resolution less than 16 bits the unused data lines are
pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input
will present the eight most significant data bits on data output
DB1 and DB8. A logic “LO” will present the least significant
byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will dupli-
cate data outputs 9 to 16.
V
H
DIR
V
L
t8
t9
V
INHIBIT
L
V
L
ENABLE
V
V
t10
H
V
Z
DATA
t11
L
BYTE
SELECT
V
L
V
H
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
V
H
DATA
V
t12
L
t13
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
PARAMETER
TMIN
200
10
TMAX
600
25
CONDITION
BUSY WIDTH VH–VH
t1
t2
RIPPLE CLOCK VH TO BUSY VH
RIPPLE CLOCK VL TO NEXT BUSY VH
BUSY VH TO DATA VH
The minimum pulse width of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next consecutive pulse.
t3
470
16
580
45
t4
t5
3
25
BUSY VH TO DATA VL
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
t6
70
140
625
670
600
110
110
140
125
INHIBIT VH TO BUSY VH
t7
485
515
–
MIN DIR VH TO BUSY VH
t8
MIN DIR VH TO BUSY VH
t9
INHIBIT VL TO DATA STABLE
ENABLE VL TO DATA VH
t10
t11
t12
t13
40
If the AD2S80A is being used in a pitch and revolution count-
ing application, the ripple and busy will need to be gated to
prevent false decrement or increment (see Figure 2).
35
ENABLE VL TO DATA VL
60
BYTE SELECT VL TO DATA STABLE
BYTE SELECT VH TO DATA STABLE
60
RIPPLE CLOCK is unaffected by INHIBIT.
REV. B
–9–
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