Datasheet > 5962-9067101MRA

5962-9067101MRA

更新时间： 2024-01-11 05:49:53

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	552K
描述
LVDT Signal Conditioner

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5962-9067101MRA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	20
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
转换器类型：	SIGNAL CONDITIONER	JESD-30 代码：	R-GDIP-T20
JESD-609代码：	e0	最大负电源电压：	-18 V
最小负电源电压：	-12 V	标称负供电电压：	-15 V
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Qualified
筛选级别：	MIL-STD-883	最大供电电压：	18 V
最小供电电压：	12 V	标称供电电压：	15 V
表面贴装：	NO	温度等级：	MILITARY
端子面层：	TIN LEAD	端子形式：	THROUGH-HOLE
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

5962-9067101MRA 数据手册

AD598

DESIGN PROCEDURE

DUAL SUPPLY OPERATION

Figure 7 shows the connection method with dual ±15 volt power

supplies and a Schaevitz E100 LVDT. This design procedure

can be used to select component values for other LVDTs as

well. The procedure is outlined in Steps 1 through 10 as follows:

The AD598 signal input, V_SEC, should be in the range of

1 V rms to 3.5 V rms for maximum AD598 linearity and

minimum noise susceptibility. Select V_SEC= 3 V rms. There-

fore, LVDT excitation voltage V_EXCshould be:

V_EXC= V_SEC× VTR = 3 × 1.75 = 5.25 V rms

Check the power supply voltages by verifying that the peak

values of V_Aand V_Bare at least 2.5 volts less than the volt-

ages at +V_Sand –V_S.

1. Determine the mechanical bandwidth required for LVDT

position measurement subsystem, f_SUBSYSTEM. For this

example, assume f_SUBSYSTEM= 250 Hz.

6. Referring to Figure 7, for V_S= ±15 V, select the value of the

amplitude determining component R1 as shown by the curve

in Figure 8.

2. Select minimum LVDT excitation frequency, approximately

10 × f_SUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.

3. Select a suitable LVDT that will operate with an excitation

frequency of 2.5 kHz. The Schaevitz E100, for instance, will

operate over a range of 50 Hz to 10 kHz and is an eligible

candidate for this example.

7. Select excitation frequency determining component C1.

C1 = 35 µF Hz/f_EXCITATION

4. Determine the sum of LVDT secondary voltages V_Aand V_B.

Energize the LVDT at its typical drive level V_PRIas shown in

the manufacturer’s data sheet (3 V rms for the E100). Set the

core displacement to its center position where V_A= V_B. Mea-

sure these values and compute their sum V_A+V_B. For the

E100, V_A+V_B= 2.70 V rms. This calculation will be used

later in determining AD598 output voltage.

V_rms

5. Determine optimum LVDT excitation voltage, V_EXC. With

the LVDT energized at its typical drive level V_PRI, set the

core displacement to its mechanical full-scale position and

measure the output V_SECof whichever secondary produces

the largest signal. Compute LVDT voltage transformation

ratio, VTR.

VTR = V_PRI/V_SEC

0.01

0.1

100

1000

For the E100, V_SEC= 1.71 V rms for V_PRI= 3 V rms.

VTR = 1.75.

R1 – kΩ

Figure 8. Excitation Voltage V_EXCvs. R1

15V

6.8µF

0.1µF

6.8µF

0.1µF

+V_S

–V_S

–15V

OFFSET 1

OFFSET 2

EXC 1

EXC 2

LEV 1

LEV 2

FREQ 1

FREQ 2

B1 FILT

B2 FILT

V_B

SIGNAL

REFERENCE

SIG REF

SIG OUT

FEEDBACK

OUT FILT

A1 FILT

A2 FILT

R_L

V_OUT

AD598

V_B

NOTE

FOR C1, C2, C3 AND C4 MYLAR

CAPACITORS ARE

RECOMMENDED. CERAMIC

CAPACITORS MAY BE

SUBSTITUTED. FOR R2, R3 AND

R4 USE STANDARD 1%

RESISTORS.

SCHAEVITZ E100

LVDT

Figure 7. Interconnection Diagram for Dual Supply Operation

–6–

REV. A

1...3 4 567 8 9...16

下载PDF

与5962-9067101MRA相关器件

型号	品牌	描述	获取价格	数据表
5962-9067501M3X	TI	ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CQCC28, CERAMIC, QCC-28	获取价格
5962-9067501MKA	ACTEL	Bus Driver, ALS Series, 1-Func, 9-Bit, True Output, TTL, CDFP24, CERAMIC, FP-24	获取价格
5962-9067501MKX	TI	ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDFP24, CERAMIC, FP-24	获取价格
5962-9067501MLA	WEDC	IC ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24, Bus Driver/Transceiver	获取价格
5962-9067501MLX	ETC	9-Bit D-Type Flip-Flop	获取价格
5962-9067502M3X	ETC	9-Bit D-Type Flip-Flop	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

5962-9067101MRA

5962-9067101MRA 技术参数

5962-9067101MRA 数据手册

与5962-9067101MRA相关器件

与5962-9067101MRA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

5962-9067101MRA

5962-9067101MRA 技术参数

5962-9067101MRA 数据手册

与5962-9067101MRA相关器件

与5962-9067101MRA相关文章

您还可以找

您在本页遇到什么问题？