Datasheet > 5962-9067101MRA

5962-9067101MRA

更新时间： 2024-01-25 00:55:28

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	552K
描述
LVDT Signal Conditioner

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

5962-9067101MRA 技术参数

生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	20
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.8
转换器类型：	SIGNAL CONDITIONER	JESD-30 代码：	R-GDIP-T20
JESD-609代码：	e0	最大负电源电压：	-18 V
最小负电源电压：	-12 V	标称负供电电压：	-15 V
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Qualified
筛选级别：	MIL-STD-883	最大供电电压：	18 V
最小供电电压：	12 V	标称供电电压：	15 V
表面贴装：	NO	温度等级：	MILITARY
端子面层：	TIN LEAD	端子形式：	THROUGH-HOLE
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

5962-9067101MRA 数据手册

AD598

a voltage proportional to position. This technique uses the pri-

mary excitation voltage as a phase reference to determine the

polarity of the output voltage. There are a number of problems

associated with this technique such as (1) producing a constant

amplitude, constant frequency excitation signal, (2) compensating

for LVDT primary to secondary phase shifts, and (3) compen-

sating for these shifts as a function of temperature and frequency.

As shown in Figure 6, the input to the integrator is [(A+B)d]B.

Since the integrator input is forced to 0, the duty cycle d =

B/(A+B).

The output comparator which produces d = B/(A+B) also con-

trols an output amplifier driven by a reference current. Duty

cycle signals d and (1–d) perform separate modulations on the

reference current as shown in Figure 6, which are summed. The

summed current, which is the output current, is I_REF× (1–2d).

The AD598 eliminates all of these problems. The AD598 does

not require a constant amplitude because it works on the ratio of

the difference and sum of the LVDT output signals. A constant

frequency signal is not necessary because the inputs are rectified

and only the sine wave carrier magnitude is processed. There is

no sensitivity to phase shift between the primary excitation and

the LVDT outputs because synchronous detection is not em-

ployed. The ratiometric principle upon which the AD598 oper-

ates requires that the sum of the LVDT secondary voltages

remains constant with LVDT stroke length. Although LVDT

manufacturers generally do not specify the relationship between

V_A+V_Band stroke length, it is recognized that some LVDTs do

not meet this requirement. In these cases a nonlinearity will

result. However, the majority of available LVDTs do in fact

meet these requirements.

Since d = B/(A+B), by substitution the output current equals

_REF× (A–B)/(A+B). This output current is then filtered and

converted to a voltage since it is forced to flow through the scal-

ing resistor R2 such that:

V_OUT= I_REF×( A – B)/(A + B)× R2

CONNECTING THE AD598

The AD598 can easily be connected for dual or single supply

operation as shown in Figures 7 and 12. The following general

design procedures demonstrate how external component values

are selected and can be used for any LVDT which meets AD598

input/output criteria.

Parameters which are set with external passive components in-

clude: excitation frequency and amplitude, AD598 system

bandwidth, and the scale factor (V/inch). Additionally, there are

optional features, offset null adjustment, filtering, and signal in-

tegration which can be used by adding external components.

The AD598 utilizes a special decoder circuit. Referring to the

block diagram and Figure 6 below, an implicit analog comput-

ing loop is employed. After rectification, the A and B signals are

multiplied by complementary duty cycle signals, d and (I–d)

respectively. The difference of these processed signals is inte-

grated and sampled by a comparator. It is the output of this

comparator that defines the original duty cycle, d, which is fed

back to the multipliers.

V TO I

INPUT

FILT

BINARY SIGNAL

d - DUTY CYCLE

0<d<1

COMP

±1

∑

INTEG

COMP

V TO I

(A+B) d–B

INPUT

FILT

1–d

^●A+B

COMP

±1

VOLTS

OUTPUT

A–B

I_REF

^●A+B

I_REF

BANDGAP

REFERENCE

∑

FILT

INTEG

V TO I

RTO

OFFSET

A–B

A+B

V_OUT

= R_SCALEx I _REF

Figure 6. Block Diagram of Decoder

–5–

REV. A

1 2 3 456 7 8...16

下载PDF

与5962-9067101MRA相关器件

型号	品牌	描述	获取价格	数据表
5962-9067501M3X	TI	ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CQCC28, CERAMIC, QCC-28	获取价格
5962-9067501MKA	ACTEL	Bus Driver, ALS Series, 1-Func, 9-Bit, True Output, TTL, CDFP24, CERAMIC, FP-24	获取价格
5962-9067501MKX	TI	ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDFP24, CERAMIC, FP-24	获取价格
5962-9067501MLA	WEDC	IC ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24, Bus Driver/Transceiver	获取价格
5962-9067501MLX	ETC	9-Bit D-Type Flip-Flop	获取价格
5962-9067502M3X	ETC	9-Bit D-Type Flip-Flop	获取价格

与5962-9067101MRA相关文章

资料手册解读：UC3842参数和管脚说明
2024-05-22

3
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
2024-05-22

4
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
2024-05-22

3
PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

11

产品中心

服务支持

精选活动

关于我们

帮助中心

5962-9067101MRA

5962-9067101MRA 技术参数

5962-9067101MRA 数据手册

与5962-9067101MRA相关器件

与5962-9067101MRA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

5962-9067101MRA

5962-9067101MRA 技术参数

5962-9067101MRA 数据手册

与5962-9067101MRA相关器件

与5962-9067101MRA相关文章

您还可以找

您在本页遇到什么问题？