Datasheet > 5962-8862801VZA

5962-8862801VZA

更新时间： 2024-02-14 14:41:40

品牌	Logo	应用领域
其他 - ETC		显示器总线控制器外围集成电路数据传输 LORA 通信时钟
页数	文件大小	规格书
52页	1271K
描述
BCRT Bus Controller/Remote Terminal/Monitor

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5962-8862801VZA 技术参数

生命周期：	Obsolete	包装说明：	CERAMIC, LCC-84
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.74	地址总线宽度：	16
边界扫描：	NO	通信协议：	MIL STD 1553B
最大数据传输速率：	0.125 MBps	外部数据总线宽度：	16
JESD-30 代码：	S-CQCC-N84	低功率模式：	NO
串行 I/O 数：	2	端子数量：	84
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	筛选级别：	MIL-STD-883
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	NO LEAD	端子位置：	QUAD
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553	Base Number Matches：	1

5962-8862801VZA 数据手册

Output Multiplexing and Self-Test Logic

This logic directs the output of the encoder to one of four

places:- Channel A outputs

- Channel B outputs

- Channel A decoders during self-test

- Channel B decoders during self-test

1.0 ARCHITECTURE AND OPERATION

The UT1553B RTI is an interface device linking a MIL-

STD-1553serialdatabusandahostmicroprocessorsystem.

The RTI’s MIL-STD-1553B interface includes encoding/

decoding logic, error detection, command recognition,

memory address control, clock, and reset circuits.

Clock and Reset Logic

Decoders

The UT1553B RTI requires a 12MHz input clock to operate

properly. The RTI provides a 2MHz output for the system

designer to use. The device provides a hardware reset pin

as well as software-generated reset.

The UT1553B RTI contains two separate free-running

decoders to insure that all redundancy requirements of MIL-

STD-1553B are met. Each decoder receives, decodes, and

veriﬁes biphase Manchester II data. Proper frequency and

edge skew are also veriﬁed.

Timer Logic

The UT1553B RTI has a built-in 730ms timer that is

activated when the encoder is about to transmit. The timer

is reset upon receipt of a valid command, master reset, or a

time-out condition.

Command Recognition Logic

The command recognition logic monitors the output of both

decoders at all times. Recognition of a valid command

causes a reset of present interface activity followed by

execution of the command. This procedure meets the

requirement for superseding valid commands.

1.1 HOST INTERFACE

Conﬁgure the RTI into the host system for either a direct

memory or transparent memory access. The following

sections discuss the system conﬁguration for each method

of memory management.

Encoder

Theencoderreceivesserialdatafromthedatatransferlogic,

converts it to Manchester II form with proper

synchronization and parity, and passes it to the output and

self-test logic.

1.1.1 Direct Memory Access

In the direct memory access conﬁguration the RTI and host

arbitrate for the shared 2K x 16 memory space. To request

access to memory the RTI asserts direct memory request

output (DMARQ); the system bus arbiter grants the RTI

access to memory by asserting the direct memory access

grantsignal(MEMCK).Thesystemarbitershouldnotassert

the MEMCK signal before the RTI has requested access to

memory (i.e., DMARQ asserted).

Data Transfer Logic

The data transfer logic provides double-buffered 16-bit

parallel-to-serial and serial-to-parallel conversion during

reception and transmission of data.

Memory Address Control

The memory address control logic controls the output of the

three-state address lines during memory access. In DMA

system implementations, the memory address control

provides RTI-generated addresses. In a pseudo-dual-port

memory conﬁguration, the memory address control logic

provides either RTI-generated or host system addressing.

Once granted access to memory, the RTI address out

(ADDR OUT(10:0)), RAM chip select (RCS), RAM read/

write(RRD/RWR), andDatabus(DATAI/O(15:0))provide

the interface signals to control the memory access. Figure

2 shows an example of a direct memory access system

conﬁguration; for clarity the interface buffers and logic are

excluded. The host microprocessor also gains access to

memory by arbitration.

Control and Error Logic

The control and error logic performs the following four

major functions:

Take care to insure that bus contention does not occur

between the host and RTIAddress buses or memory control

signals. To place the RTI Address Out bus in a high

impedance state negate the ADOEN input pin. Also note

thatoutputsRCSandRRD/RWRarenotthree-stateoutputs.

When the RTI is not writing to memory, bidirectional Data

bus DATA I/O(15:0) is an input (i.e., not actively driving

the bus).

Interface control for proper processing of MIL-

STD-1553B commands

Error checking of both MIL-STD-1553B data and

RTI operation

Memory control (DMA or pseudo-dual-port) for

proper data transfer

Operational status and control signal generation

RTI-3

1 234 5 6 7...52

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与5962-8862801VZA相关器件

型号	品牌	获取价格	描述	数据表
5962-8862801VZC	ETC	获取价格	BCRT Bus Controller/Remote Terminal/Monitor
5962-8862801VZX	ETC	获取价格	BCRT Bus Controller/Remote Terminal/Monitor
5962-8862801XA	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
5962-8862801-XA	ETC	获取价格	BCRT Bus Controller/Remote Terminal/Monitor
5962-8862801XC	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
5962-8862801-XC	ETC	获取价格	BCRT Bus Controller/Remote Terminal/Monitor
5962-8862801-XX	ETC	获取价格	BCRT Bus Controller/Remote Terminal/Monitor
5962-8862801YA	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU
5962-8862801-YA	ETC	获取价格	BCRT Bus Controller/Remote Terminal/Monitor
5962-8862801YC	ETC	获取价格	MIL-STD-1553/ARINC Bus Controller/RTU

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