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5962-8862801VZA PDF预览

5962-8862801VZA

更新时间： 2024-02-27 02:10:03
品牌 Logo 应用领域
其他 - ETC 显示器总线控制器外围集成电路数据传输LORA通信时钟
页数 文件大小 规格书
52页 1271K
描述
BCRT Bus Controller/Remote Terminal/Monitor

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5962-8862801VZA 技术参数

生命周期：Obsolete包装说明：CERAMIC, LCC-84
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.74地址总线宽度：16
边界扫描：NO通信协议：MIL STD 1553B
最大数据传输速率：0.125 MBps外部数据总线宽度：16
JESD-30 代码：S-CQCC-N84低功率模式：NO
串行 I/O 数：2端子数量：84
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not Qualified筛选级别：MIL-STD-883
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：NO LEAD端子位置：QUAD
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553Base Number Matches：1

5962-8862801VZA 数据手册

 浏览型号5962-8862801VZA的Datasheet PDF文件第1页浏览型号5962-8862801VZA的Datasheet PDF文件第2页浏览型号5962-8862801VZA的Datasheet PDF文件第3页浏览型号5962-8862801VZA的Datasheet PDF文件第5页浏览型号5962-8862801VZA的Datasheet PDF文件第6页浏览型号5962-8862801VZA的Datasheet PDF文件第7页 
Shared  
Memory  
CONTROL  
CONTROL  
Host  
Computer  
RTI  
UT1553B  
DATA(15:0)  
ADDR(10:0)  
DMA  
CONTROLLER  
Figure 2. Direct Memory Access Configuration  
The host microprocessor gains access to the RTI internal  
registers by controlling input pins CS, CTRL, ADDR IN  
(10:0), and RD/WR. During message processing the host  
microprocessorshouldlimitaccesstoRTIinternalregisters.  
The host microprocessor gains access to the RTI internal  
registers by controlling input pins CS, CTRL, ADDR IN  
(10:0), and RD/WR. During message processing the host  
microprocessorshouldlimitaccesstoRTIinternalregisters.  
The host should not assert CS while the RTI is performing  
a memory access.  
1.1.2 Transparent Memory Access  
Configured in the transparent memory mode the host  
microprocessor accesses shared memory through the RTI.  
Arbitration for access to the bus is performed as discussed  
in section 1.1.1 of this document.  
1.2 Internal Register Description  
The RTI uses three internal registers to allow the host to  
control the RTI operation and monitor its status. The host  
uses the following inputs Control (CTRL), Chip Select  
(CS), Read/Write (RD/WR), and ADDR IN (0) to read the  
16-bitSystemRegisterorwritetothe8-bitControlRegister.  
The Control Register toggles bits in the MIL-STD-1553B  
status word, enables biphase inputs, selects terminal active  
flag, and puts the part in self-test. The System Register  
supplies operational status of the UT1553B RTI to the host.  
The Last Command Register saves the command word for  
a Transmit Last Command mode code, along with  
operational status from the System Register.  
When granted access to memory, the RTI asserts memory  
control signals ADDR OUT(10:0), RCS, and RRD/RWR.  
For host-controlled memory accesses the RAM memory  
address from the host is propagated from theAddress In bus  
ADDRIN(10:0)totheAddressOutbusADDROUT(10:0).  
MemorycontrolsignalsRD/WRandCSarealsopropagated  
through the RTI as RRD/RWR and RCS. Input CTRL is  
negated during all transparent memory accesses to prevent  
the RTI from inadvertently performing an internal register  
access or software reset. While CS is asserted, the RTI’s  
bidirectional Data bus DATA I/O (15:0) is an input (i.e., not  
actively driving bus).  
DATA(15:0)  
CONTROL  
CONTROL  
Host  
RTI  
UT1553B  
Shared  
Memory  
Computer  
DATA I/O (15:0)  
ADDR OUT (10:0)  
ADDR IN (10:0)  
DMA  
CONTROLLER  
Figure 3. Transparent Memory Access Configuration  
Control Register (Write Only)  
RTI-4  
1234567...52

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