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5962-8769701BRA PDF预览

5962-8769701BRA

更新时间: 2024-11-05 06:18:31
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 226K
描述
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20, CERDIP-20

5962-8769701BRA 数据手册

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February 1999  
54AC377 54ACT377  
Octal D Flip-Flop with Clock Enable  
n Ideal for addressable register applications  
n Clock enable for address and data synchronization  
applications  
n Eight edge-triggered D flip-flops  
n Buffered common clock  
General Description  
The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops  
with individual D inputs and Q outputs. The common buff-  
ered Clock (CP) input loads all flip-flops simultaneously,  
when the Clock Enable (CE) is LOW.  
n Outputs source/sink 24 mA  
n See ’273 for master reset version  
n See ’373 for transparent latch version  
n See ’374 for TRI-STATE® version  
n ’ACT377 has TTL-compatible inputs  
n Standard Microcircuit Drawing (SMD)  
— ’AC377: 5962-88702  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
The CE input must be stable only one setup time prior to the  
LOW-to-HIGH clock transition for predictable operation.  
Features  
n ICC reduced by 50%  
— ’ACT377: 5962-87697  
Logic Symbols  
IEEE/IEC  
DS100290-1  
DS100290-2  
Pin  
Description  
Names  
D0–D7  
CE  
Data Inputs  
Clock Enable (Active LOW)  
Data Outputs  
Q0–Q7  
CP  
Clock Pulse Input  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS100290  
www.national.com  

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