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5962-8768102V2X PDF预览

5962-8768102V2X

更新时间： 2024-02-11 18:27:27
品牌 Logo 应用领域
德州仪器 - TI 稳压器开关式稳压器或控制器电源电路开关式控制器
页数 文件大小 规格书
15页 302K
描述
2.2A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, CQCC20, CERAMIC, LCC-20

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5962-8768102V2X 技术参数

生命周期：Active零件包装代码：QLCC
包装说明：QCCN,针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5
其他特性：CONFIGURABLE CURRENT MODE OPERATION模拟集成电路 - 其他类型：SWITCHING CONTROLLER
控制模式：VOLTAGE-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：20 V最小输入电压：8.8 V
标称输入电压：12 VJESD-30 代码：S-CQCC-N20
长度：8.89 mm功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C最大输出电流：2.2 A
最大输出电压：5.15 V最小输出电压：5.05 V
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Qualified
筛选级别：MIL-PRF-38535 Class V座面最大高度：2.03 mm
最大供电电流 (Isup)：36 mA标称供电电压 (Vsup)：12 V
表面贴装：YES切换器配置：PUSH-PULL
最大切换频率：1000 kHz技术：BICMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：8.89 mm
Base Number Matches：1

5962-8768102V2X 数据手册

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www.ti.com  
SLUS334C − AUGUST 1995 − REVISED AUGUST 2004  
HIGH CURRENT OUTPUTS  
Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak current into a  
capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC)  
and power ground (PGND) pins help decouple the device’s analog circuitry from the high-power gate drive noise. The use  
of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND  
are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive  
load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT  
USE standard silicon diodes.  
Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B devices. These  
can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each output for a combined peak  
current of 4 A.  
UDG−95114  
Figure 12. Power MOSFET Drive Circuit  
GROUND PLANES  
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the  
chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents  
associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can  
be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high  
di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high  
frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection  
for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode  
to both VCC and PGND. Nothing else should be connected to power ground.  
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low  
ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be  
bypassed to the signal ground plane.  
10  
1...78910111213...15

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