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5962-8685913LA PDF预览

5962-8685913LA

更新时间: 2024-02-29 23:23:57
品牌 Logo 应用领域
MICROSS 静态存储器内存集成电路
页数 文件大小 规格书
11页 156K
描述
Standard SRAM, 16KX4, 55ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24

5962-8685913LA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP,针数:24
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.66
最长访问时间:55 nsJESD-30 代码:R-GDIP-T24
JESD-609代码:e0长度:32.004 mm
内存密度:65536 bit内存集成电路类型:OTHER SRAM
内存宽度:4功能数量:1
端子数量:24字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:16KX4封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
认证状态:Qualified筛选级别:MIL-STD-883
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

5962-8685913LA 数据手册

 浏览型号5962-8685913LA的Datasheet PDF文件第2页浏览型号5962-8685913LA的Datasheet PDF文件第3页浏览型号5962-8685913LA的Datasheet PDF文件第4页浏览型号5962-8685913LA的Datasheet PDF文件第5页浏览型号5962-8685913LA的Datasheet PDF文件第6页浏览型号5962-8685913LA的Datasheet PDF文件第7页 
SRAM  
MT5C6405  
PIN ASSIGNMENT  
16K x 4 SRAM  
SRAM MEMORY ARRAY  
(Top View)  
24-Pin DIP (C)  
(300 MIL)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
• SMD 5962-86859  
A5  
A6  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Vcc  
A4  
MIL-STD-883  
A7  
A3  
A8  
A2  
A9  
A1  
A10  
A11  
A12  
A13  
CE\ 10  
OE\ 11  
Vss 12  
A0  
NC  
FEATURES  
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns  
• Battery Backup: 2V data retention  
• High-performance, low-power CMOS double-metal  
process  
DQ4  
DQ3  
DQ2  
DQ1  
WE\  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\  
• All inputs and outputs are TTL compatible  
28-Pin LCC (EC)  
3
2 1 28 27  
OPTIONS  
• Timing  
MARKING  
26  
25  
24  
23  
22  
21  
20  
NC  
A4  
A3  
A2  
A1  
A6  
A7  
A8  
4
5
6
7
8
A9  
12ns access  
15ns access  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access  
70ns access  
-12  
-15  
-20  
-25  
A10  
A11  
A12  
A13  
CE\  
A0  
DQ4  
9
10  
11  
12  
19 DQ3  
18  
DQ2  
13 14 15 16 17  
-35  
-45*  
-55*  
-70*  
• Package(s)  
Ceramic DIP (300 mil) C  
Ceramic LCC  
GENERAL DESCRIPTION  
No. 106  
E C  
The Micross Components SRAM family employs high-  
speed, low-power CMOS designs using a four-transistor mem-  
ory cell. Austin Semiconductor SRAMs are fabricated using  
double-layer metal, double-layer polysilicon technology.  
For exibility in high-speed memory applications, Micross  
Components offers chip enable (CE\) and output enable (OE\)  
capability. These enhancements can place the outputs in High-Z  
for additional exibility in system design.  
No. 204  
• Operating Temperature Ranges  
Industrial (-40oC to +85oC)  
Military (-55oC to +125oC)  
IT  
XT  
• 2V data retention/low power  
L
*Electrical characteristics identical to those provided for the 35ns ac-  
cess devices.  
Writing to these devices is accomplished when write enable  
(WE\) and CE\ inputs are both LOW. Reading is accomplished  
when WE\ remains HIGH and CE\ and OE\ go LOW. The  
device offers a reduced power standby mode when disabled.  
This allows system designs to achieve low standby power  
requirements.  
For more products and information  
please visit our web site at  
www.miross.com  
All devices operate from a single +5V power supply and all  
inputs and outputs are fully TTL compatible.  
Micross Components reserves the right to change products or specications without notice.  
MT5C6405  
Rev. 2.2 01/10  
1

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