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5962-0924001VXC PDF预览

5962-0924001VXC

更新时间: 2024-01-07 07:18:08
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
46页 1034K
描述
12-Bit, 1-GSPS Analog-to-Digital Converter

5962-0924001VXC 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFP-100针数:100
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.44
Is Samacsys:N最小模拟输入电压:-2 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-CQFP-F100
长度:19.05 mm最大线性误差 (EL):0.1099%
模拟输入通道数量:1位数:12
功能数量:1端子数量:100
最高工作温度:125 °C最低工作温度:-55 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:HGQFF
封装等效代码:TPAK100,2.0SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, GUARD RING峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3,5 V认证状态:Qualified
采样速率:1000 MHz采样并保持/跟踪并保持:TRACK
筛选级别:MIL-STD-883 Class V座面最大高度:3.15 mm
子类别:Analog to Digital Converters最大压摆率:255 mA
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR温度等级:MILITARY
端子形式:FLAT端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:19.05 mmBase Number Matches:1

5962-0924001VXC 数据手册

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ADS5400-SP  
www.ti.com  
SLAS669C SEPTEMBER 2010REVISED AUGUST 2012  
Timing Diagrams  
N
DIFFERENTIAL  
ANALOG INPUT  
(INP-INN)  
Aperture  
delay  
ta  
N+1  
N+2  
Sample N and RESET pulse  
captured here  
N
output  
N+1  
output  
tCLKH  
tCLKL  
CLKINP  
tRH  
tRSU  
CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2  
tPD-CLKDIV2  
)
RESETP  
Phase 0: CLKOUT in desired  
CLKOUTAP state after power up  
Phase 1: misaligned by  
1 clock after power up  
tPD-ADATA  
t
su  
Latency of N and SYNCOUTA are matched to 7 CLKIN cycles  
t
h
N-1  
N
N+1 N+2  
DATA BUS A  
If SYNC mode is enabled,  
the OVRA pins become SYNCOUTA pins  
SYNCOUTA  
(OVRA pins)  
Sync  
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase  
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT  
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of  
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the  
CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that  
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a  
SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.  
Figure 1. Single Bus Mode  
Copyright © 2010–2012, Texas Instruments Incorporated  
9
Product Folder Links: ADS5400-SP  
 

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