5秒后页面跳转
5962-0924001VXC PDF预览

5962-0924001VXC

更新时间: 2024-02-12 01:00:24
品牌 Logo 应用领域
德州仪器 - TI 转换器模数转换器
页数 文件大小 规格书
46页 1034K
描述
12-Bit, 1-GSPS Analog-to-Digital Converter

5962-0924001VXC 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFP-100针数:100
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.44
Is Samacsys:N最小模拟输入电压:-2 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-CQFP-F100
长度:19.05 mm最大线性误差 (EL):0.1099%
模拟输入通道数量:1位数:12
功能数量:1端子数量:100
最高工作温度:125 °C最低工作温度:-55 °C
输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:HGQFF
封装等效代码:TPAK100,2.0SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, GUARD RING峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3,5 V认证状态:Qualified
采样速率:1000 MHz采样并保持/跟踪并保持:TRACK
筛选级别:MIL-STD-883 Class V座面最大高度:3.15 mm
子类别:Analog to Digital Converters最大压摆率:255 mA
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR温度等级:MILITARY
端子形式:FLAT端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:19.05 mmBase Number Matches:1

5962-0924001VXC 数据手册

 浏览型号5962-0924001VXC的Datasheet PDF文件第4页浏览型号5962-0924001VXC的Datasheet PDF文件第5页浏览型号5962-0924001VXC的Datasheet PDF文件第6页浏览型号5962-0924001VXC的Datasheet PDF文件第8页浏览型号5962-0924001VXC的Datasheet PDF文件第9页浏览型号5962-0924001VXC的Datasheet PDF文件第10页 
ADS5400-SP  
www.ti.com  
SLAS669C SEPTEMBER 2010REVISED AUGUST 2012  
TIMING CHARACTERISTICS(1) (continued)  
Typical values at TA = 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,  
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock  
(unless otherwise noted)  
PARAMETER  
TEST CONDITIONS/NOTES  
MIN  
TYP  
MAX UNIT  
LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)(2)  
tCLK  
Clock period  
1
0.45  
0.45  
10  
ns  
ns  
ns  
tCLKH  
tCLKL  
Clock pulse duration, high  
Clock pulse duration, low  
Assuming worst case 45/55 duty cycle  
Assuming worst case 55/45 duty cycle  
CLKIN rising to CLKOUT rising in divide by 2  
mode  
1200  
1200  
tPD-CLKDIV2  
tPD-CLKDIV4  
tPD-ADATA  
tPD-BDATA  
Clock propagation delay  
Clock propagation delay  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
CLKIN rising to CLKOUT rising in divide by 4  
mode  
Bus A data propagation  
delay  
1400  
1400  
CLKIN falling to Data Output transition  
Bus B data propagation  
delay  
Data valid to CLKOUT edge, 50% CLKIN duty  
cycle  
(3)  
tSU-SBM  
Setup time, single bus mode  
Hold time, single bus mode  
Setup time, dual bus mode  
Hold time, dual bus mode  
290 (tCLK/2) - 185  
CLKOUT edge to Data invalid, 50% CLKIN duty  
cycle  
tH-SBM  
tSU-DBM  
tH-DBM  
410  
550  
(tCLK/2) - 65  
tCLK - 425  
tCLK + 175  
Data valid to CLKOUT edge, 50% CLKIN duty  
cycle  
CLKOUT edge to Data invalid, 50% CLKIN duty  
cycle  
1150  
tr  
tf  
LVDS output rise time  
LVDS output fall time  
400  
400  
ps  
ps  
Measured 20% to 80%  
LVDS INPUT TIMING (RESETIN)  
tRSU  
tRH  
RESET setup time  
RESETP going HIGH to CLKINP going LOW  
CLKINP going LOW to RESETP going LOW  
Differential  
325  
325  
ps  
ps  
pF  
µA  
RESET hold time  
RESET input capacitance  
RESET input current  
1
±1  
SERIAL INTERFACE TIMING  
tS-SDENB  
tH-SDENB  
tS-SDIO  
tH-SDIO  
fSCLK  
tSCLK  
tSCLKH  
tSCLKL  
tr  
Setup time, serial enable  
SDENB falling to SCLK rising  
SCLK falling to SENDB rising  
SDIO valid to SCLK rising  
20  
25  
10  
10  
ns  
ns  
Hold time, serial enable  
Setup time, SDIO  
Hold time, SDIO  
Frequency  
ns  
SCLK rising to SDIO transition  
ns  
10  
MHz  
ns  
SCLK period  
100  
40  
Minimum SCLK high time  
Minimum SCLK low time  
Rise time  
ns  
40  
ns  
10pF  
10pF  
10  
10  
ns  
tf  
Fall time  
ns  
Data output (SDO/SDIO) delay after SCLK  
falling, 10pF load  
tDDATA  
Data output delay  
75  
ns  
(2) LVDS output timing measured with a differential 100Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance  
is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing  
parameters are relative to the device pins, with the loading as stated.  
(3) In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum  
700ps of data valid window, with 300ps of uncertainity.  
Copyright © 2010–2012, Texas Instruments Incorporated  
7
Product Folder Links: ADS5400-SP  
 

与5962-0924001VXC相关器件

型号 品牌 描述 获取价格 数据表
5962-1022101VSC TI 耐辐射 QMLV、3V 至 6.3V 输入、6A 同步降压转换器 | HKH | 20 |

获取价格

5962-1022102VSC TI 耐辐射 QMLV、3V 至 7V 输入、6A 同步降压转换器 | HKH | 20 | -

获取价格

5962-1022401KXA INFINEON Analog Circuit, Hybrid,

获取价格

5962-1022401KXC INFINEON Analog Circuit, Hybrid,

获取价格

5962-1023503KYA INFINEON Fixed Positive LDO Regulator, 1.8V, 0.4V Dropout, Hybrid, FP-8

获取价格

5962-1023504KXA INFINEON Fixed Positive LDO Regulator, 2.5V, 0.4V Dropout, Hybrid, FP-8

获取价格