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5962-0824503HXC PDF预览

5962-0824503HXC

更新时间: 2024-01-16 03:35:29
品牌 Logo 应用领域
MICROSS 内存集成电路
页数 文件大小 规格书
29页 363K
描述
Flash, 2MX32, 90ns, CQFP68, QFP-68

5962-0824503HXC 技术参数

生命周期:Active零件包装代码:QFP
包装说明:QFP,针数:68
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.51风险等级:5.67
最长访问时间:90 ns其他特性:BOTTOM BOOT BLOCK
启动块:BOTTOMJESD-30 代码:R-CQFP-G68
长度:24.028 mm内存密度:67108864 bit
内存集成电路类型:FLASH内存宽度:32
功能数量:1端子数量:68
字数:2097152 words字数代码:2000000
工作模式:ASYNCHRONOUS组织:2MX32
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QFP
封装形状:RECTANGULAR封装形式:FLATPACK
并行/串行:PARALLEL编程电压:3 V
认证状态:Qualified筛选级别:MIL-STD-883
座面最大高度:3.56 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
端子形式:GULL WING端子节距:1.27 mm
端子位置:QUAD宽度:22.352 mm
Base Number Matches:1

5962-0824503HXC 数据手册

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FLASH  
AS8FLC2M32  
A system reset would then also reset the FLASH device,  
enabling the system microprocessor to read the boot-up  
rmware from the FLASH memory array. The device offers two  
power-saving features. When addresses have been stable for a  
specied amount of time, the device enters the AUTOMATIC  
SLEEP MODE. The system can also place the device into the  
STANDBY mode. Power consumption is greatly reduced in  
both these modes.  
the power transition. No command is necessary in this mode to  
obtain array data. Standard microprocessor read cycles that  
assert valid data on the device address inputs produce valid  
data on the data outputs. The device remains enabled for read  
access until the command register contents are altered.  
See READING ARRAY DATA for more information. Refer  
to AC Read Operations table data for timing specications  
relevant to this operational mode.  
Device Bus Operations  
This section describes the use of the command register for setting  
and controlling the bus operations. The command register itself  
does not occupy any addressable memory locations. The register  
is composed of a series of latches that store the commands,  
addresses and data information needed to execute the indicated  
command. The contents of the register serve as the input to the  
internal state machine. The state machine output dictates the  
function of the device. Table 1 lists the device bus operations,  
the inputs and control/stimulus levels they require, and the  
resulting output. The following subsections describe each of  
these operations in further detail.  
Writing Commands/Command Sequences  
To WRITE a command or command sequence, the system must  
drive CSx\, WEx\ to VIL and OE\ to VIH.  
An ERASE command operation can erase one sector, multiple  
sectors, or the entire array. Table 2 indicates the address  
space contained within each sector within the array. A sector  
address  
consists of the address bits required to uniquely select a  
sector.  
The “Command Denitions” section has details on erasure  
of a single, multiple sectors, the entire array or suspending/  
resuming the erase operation.  
Requirements for Reading Array Data  
To read array data from the outputs, the system must drive the  
CSx\ and OE\ pins to VIL. Chip Select CSx\ is the power and  
chip select control of the byte or bytes targeted by the system  
(user). Output Enable [OE\] is the output control and gates array  
data to the output pins. Write (byte) Enables [WEx\] should  
remain at VIH levels.  
After the system writes the autoselect command sequence, the  
device enters the autoselect mode. The system can then read  
autoselect codes from the internal register (which is separate  
from the memory array) on each of the Data input/output bits  
within each byte of the MCM FLASH array. Standard read  
cycle timings apply in this mode. Refer to the Autoselect  
Mode and Autoselect Command Sequence sections for more  
information.  
The internal state machine is set for reading array data upon  
device power-up, or after a HARDWARE RESET. This ensures  
that no spurious alteration of the memory content occurs  
during  
ICC2 in the DC Characteristics table represents that active  
current specification for the WRITE mode. The AC  
Characteristics section contains timing specications for Write  
Operations.  
Table 1  
RESET\  
CS1\  
L
CS2\  
H
CS3\  
H
CS4\  
H
WE1\ WE2\ WE3\ WE4\ OE\  
OPERATION  
ADDRESSES  
DATA BUS (DQ0-DQX)  
D0-D7 Out  
H
L
H
H
D8-D15 Out  
D16-D31 Out  
D24-D31 Out  
D0-D31 Out  
D0-D7 In  
H
H
H
H
H
L
READ  
A0-Ax In  
H
H
L
H
H
H
H
L
L
L
L
L
L
H
H
H
L
H
H
H
L
H
L
H
H
L
H
H
H
L
H
L
H
H
D8-D15 In  
H
H
WRITE  
A0-Ax In  
H
H
L
H
H
H
L
D16-D31 In  
D24-D31 In  
D0-D31 In  
H
H
H
L
H
L
L
L
L
L
L
VCC +/- 0.3V VCC +/- 0.3V VCC +/- 0.3V VCC +/- 0.3V VCC +/- 0.3V  
X
H
X
X
H
X
X
H
X
X
H
X
X
H
X
Standby  
Output Diable  
Reset  
X
X
X
X
L
L
L
L
L
X
X
X
X
SECTOR ADDRESS  
A7=L, A2=H, A1=L  
D
D
IN, DOUT  
VID  
L
L
L
L
L
L
L
L
H
Sector Protect  
SECTOR ADDRESS  
A7=L, A2=H, A1=L  
AIN  
IN, DOUT  
DIN  
VID  
VID  
L
L
L
L
L
L
L
L
H
X
Sector Unprotect  
X
X
X
X
X
X
X
X
Temporary Sector Unprotect  
Legend  
Notes  
L=Logic=VIL, H=Logic High=VIH, VID=12.0 +/-0.5V, X= Don't Care, AIN=Address In, DOUT=Data Out  
Micross Components reserves the right to change products or specications without notice.  
AS8FLC2M32B  
Rev. 1.6 05/11  
3

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