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5962-0824501HYA PDF预览

5962-0824501HYA

更新时间： 2024-02-10 05:53:33
品牌 Logo 应用领域
MICROSS 内存集成电路
页数 文件大小 规格书
29页 363K
描述
Flash, 2MX32, 120ns, CPGA66, HIP-66

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5962-0824501HYA 技术参数

生命周期：Obsolete零件包装代码：PGA
包装说明：PGA,针数：66
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.32.00.51风险等级：5.77
最长访问时间：120 ns其他特性：BOTTOM BOOT BLOCK
启动块：BOTTOMJESD-30 代码：S-CPGA-P66
长度：30.099 mm内存密度：67108864 bit
内存集成电路类型：FLASH内存宽度：32
功能数量：1端子数量：66
字数：2097152 words字数代码：2000000
工作模式：ASYNCHRONOUS组织：2MX32
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：PGA
封装形状：SQUARE封装形式：GRID ARRAY
并行/串行：PARALLEL编程电压：3 V
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：6.223 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
端子形式：PIN/PEG端子节距：2.54 mm
端子位置：PERPENDICULAR类型：NOR TYPE
宽度：30.099 mmBase Number Matches：1

5962-0824501HYA 数据手册

 浏览型号5962-0824501HYA的Datasheet PDF文件第1页浏览型号5962-0824501HYA的Datasheet PDF文件第3页浏览型号5962-0824501HYA的Datasheet PDF文件第4页浏览型号5962-0824501HYA的Datasheet PDF文件第5页浏览型号5962-0824501HYA的Datasheet PDF文件第6页浏览型号5962-0824501HYA的Datasheet PDF文件第7页 
FLASH  
AS8FLC2M32  
BLOCK DIAGRAM  
before executing the erase operation. During erasure, the  
device automatically times the erase pulse widths and verifies  
proper cell margin.  
68-Ld. CQFP, Package "QT"  
CS1\  
CS2\  
WE2\  
CS3\  
CS4\  
WE4\  
WE1\  
WE3\  
RESET\  
OE\  
A0-Ax  
The host system can detect whether a program or erase  
operation is complete by reading the DQ7 (Data\ Polling) and  
DQ6 (toggle) STATUS BITS. After a program or erase cycle  
has been completed, the device is ready to read array data or  
accept another command.  
M x 8  
2
M x 8  
2
M x 8  
2
M x 8  
2
The SECTOR ERASE ARCHITECTURE allows memory  
sectors to be erased and reprogrammed without affecting the  
data contents of other sectors. The device is fully erased when  
shipped from Micross.  
DQ  
DQ  
0-7  
DQ  
16-23  
DQ  
24-31  
8-15  
BLOCK DIAGRAM  
P
66-Ld. HIP, Package "H"  
Hardware data protection measures include a low VCC  
detector that automatically inhibits WRITE operations during  
power transitions. The hardware sector protection features  
disables both program and erase operation in any combination  
of the sectors of memory. This can be achieved in-system or  
via specially adapted commercial programming equipment.  
CS1\  
CS2\ CS3\  
CS4\  
WE\  
RESET\  
OE\  
A0-Ax  
2
M x 8  
2
M x 8  
2
M x 8  
2M x 8  
The ERASE SUSPEND feature enables the user to put erase  
on hold for any period of time to read data from, or program  
data to, any sector which is not selected for erasure. True  
BACKGROUND ERASE can thus be achieved.  
DQ  
16-23  
DQ  
24-31  
D
Q
0-7  
8-15  
DQ  
The device requires only a single 3.3volt power supply for  
both READ and WRITE operations. Internally generated and  
regulated voltages are provided for the program and erase  
functions.  
The HARDWARE RESET\ PIN terminates any operation  
in progress and resets the internal state machine to a READ  
operation. The RESET\ pin may be tied to the system reset  
circuitry.  
The device is entirely command set compatible with the  
JEDEC SINGLE POWER FLASH STANDARD. Com-  
mands are written to the command register using standard  
microprocessor write timings. Register contents serve as  
input to an internal state-machine that controls the erase and  
programming circuitry. Write cycles also internally latch  
addresses and data required for the programming or erase  
function(s). Reading data out of the array is similar to reading  
from other electrically programmable devices.  
LOGIC DIAGRAM (Byte)  
VCC  
GND  
DQ (byte)  
I/O Buffers  
Data Latch  
State  
Control  
RESET\  
Erase Voltage  
Generator  
Command  
Register  
WEx\  
Device programming occurs by executing the program  
command sequence. This initiates the EMBEDDED  
PROGRAM algorithm that automatically times the WRITE  
PULSE widths and cycle and verifies each cell for proper  
cell margins. The UNLOCK BYPASS mode facilitates faster  
programming times by requiring only two WRITE cycles to  
program data instead of four.  
PGM Voltage  
Generator  
Chip Enable  
Output Enable  
Logic  
CSx\  
OE\  
Sector  
Switches  
Y-Decoder  
Y-Gating  
VCC Detector  
Timer  
X-Decoder  
Cell Matrix  
A0-Ax  
Device erasure occurs by executing the erase command  
sequence. This initiates the Embedded Erase algorithm, an  
internal algorithm that automatically pre-programs the array  
AS8FLC2M32B  
Micross Components reserves the right to change products or specifications without notice.  
Rev. 1.6 05/11  
2
1234567...29

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