Datasheet > 570AAC000106DG

570AAC000106DG

更新时间： 2024-11-08 09:32:39

品牌	Logo	应用领域
芯科 - SILICON		振荡器
页数	文件大小	规格书
36页	562K
描述
LVPECL Output Clock Oscillator,

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中文翻译

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技术参数
数据手册

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570AAC000106DG 技术参数

是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	compliant	风险等级：	5.67
振荡器类型：	LVPECL	Base Number Matches：	1

570AAC000106DG 数据手册

Si570/Si571

10 MHZ TO 1.4 GHZ I²C PROGRAMMABLE XO/VCXO

Features



Any programmable output

frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz



Internal fixed crystal frequency

ensures high reliability and low

aging

Si5602



Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant

1.8, 2.5, or 3.3 V supply



I C serial interface

3rd generation DSPLL with superior

jitter performance

3x better frequency stability than

SAW-based oscillators



Applications

Ordering Information:



SONET/SDH

xDSL

10 GbE LAN/WAN

ATE



High performance

instrumentation

Low-jitter clock generation

Optical modules

Clock and data recovery

See page 31.



Pin Assignments:

See page 30.

Description

(Top View)

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-

programmable to any output frequency from 10 to 945 MHz and select frequencies

SDA

V_DD

to 1400 MHz with <1 ppb resolution. The device is programmed via an I C serial

interface. Unlike traditional XO/VCXOs where a different crystal is required for

each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL

clock synthesis IC to provide any-frequency operation. This IC-based approach

allows the crystal resonator to provide exceptional frequency stability and

reliability. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems.

CLK–

CLK+

GND

SCL

Functional Block Diagram

Si570

CLK- CLK+

V_DD

SDA

V_C

V_DD

10-1400 MHz

DSPLL^Clock

Synthesis

Fixed

Frequency

SDA

SCL

CLK–

CLK+

Si571 only

GND

ADC

SCL

GND

Si571

V_C

Rev. 1.6 6/18

Si570/Si571

12 3 4 5 6 7...36

中文翻译

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