™
Ultra Series Crystal Oscillator
Si564 Data Sheet
Ultra Low Jitter I2C Programmable XO (90 fs), 0.2 to
3000 MHz
KEY FEATURES
• I2C programmable to any frequency from 0.2 to
3000 MHz with < 1 ppb resolution
The Si564 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th
generation DSPLL® technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is user-programmed via simple
I2C commands to provide any frequency from 0.2 to 3000 MHz with <1 ppb
resolution and maintains exceptionally low jitter for both integer and fraction-
al frequencies across its operating range. The Si564 offers excellent reliabili-
ty and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection,
simplifying the task of generating low jitter clocks in noisy systems that use
switched-mode power supplies. The Si564 has a dramatically simplified sup-
ply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal
is required for each output frequency, the Si564 uses one simple crystal and
a DSPLL IC-based approach to provide the desired output frequency. The
Si564 is factory-configurable for a wide variety of user specifications, includ-
ing startup frequency, I2C address, output format, and OE pin location/
polarity. Specific configurations are factory-programmed at time of shipment,
eliminating the long lead times associated with custom oscillators.
• Ultra low jitter: 90 fs RMS Typ (12 kHz – 20 MHz)
• Configure up to 4 pin-selectable startup frequencies
• I2C interface supports 100 kbps, 400 kbps, and 1
Mbps (Fast Mode Plus)
• Excellent PSRR and supply noise immunity: –80
dBc Typ
• 3.3 V, 2.5 V and 1.8 V V supply operation from
DD
the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and Dual
CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics, PAM4
• 10G/40G/100G optical ethernet
Pin Assignments
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, search acceleration
• Test and measurement
SDA
7
OE/FS/NC
NC/OE/FS
GND
1
2
3
6
5
4
VDD
CLK–
CLK+
• FPGA/ASIC clocking
8
SCL
(Top View)
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