Datasheet > 552FE622M080BGR

552FE622M080BGR

更新时间： 2024-11-13 03:03:11

品牌	Logo	应用领域
芯科 - SILICON		石英晶振压控振荡器
页数	文件大小	规格书
8页	187K
描述
DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

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552FE622M080BGR 数据手册

Si552

PRELIMINARY DATA SHEET

DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

Features

Available with any-rate output

3x better frequency stability than

SAW-based oscillators

frequencies from 10 to 945 MHz and

selected frequencies to 1.4 GHz

Two selectable output frequencies

Industry-standard 7x5 mm package

Available CMOS, LVPECL, LVDS &

CML outputs

Si5602

3rd generation DSPLL with

superior jitter performance

Internal fixed crystal frequency

ensures high reliability and low

aging

Lead-free/RoHS-compliant

Applications

Ordering Information:

SONET / SDH

xDSL

10 GbE LAN / WAN

Low jitter clock generation

Optical Modules

Test and Measurement

See page 7.

Description

The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced

DSPLL circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC based approach allows the crystal resonator to be optimized for superior

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments often found in communication

systems. The Si552 IC based VCXO is factory configurable for a wide

variety of user specifications including frequency, supply voltage and output

format. Specific configurations are factory programmed into the Si552 at

time of shipment, thereby eliminating the long lead times associated with

custom oscillators.

Functional Block Diagram

V_DD

CLK-

CLK+

Any-rate

10–1400 MHz

DSPLL™

Fixed

Frequency XO

Clock Synthesis

ADC

V_C

GND

Preliminary Rev. 0.2 8/05

Si552

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4 5 6 7 8

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