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552AE000303DGR PDF预览

552AE000303DGR

更新时间: 2024-11-14 05:21:23
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
15页 122K
描述
Oscillator, 10MHz Min, 945MHz Max, 167.331646MHz Nom

552AE000303DGR 数据手册

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Si552  
REVISION D  
DUAL FREQUENCY VOLTAGE-CONTROLLED CRYSTAL  
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ  
Features  
Available with any-rate output  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
frequencies from 10–945 MHz and  
selected frequencies to 1.4 GHz  
Two selectable output frequencies  
®
3rd generation DSPLL with superior  
jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 10.  
SONET/SDH  
xDSL  
10 GbE LAN/WAN  
Low-jitter clock generation  
Optical modules  
Clock and data recovery  
Pin Assignments:  
See page 9.  
Description  
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced  
DSPLL circuitry to provide a very low jitter clock for all output frequencies.  
(Top View)  
®
The Si552 is available with any-rate output frequency from 10 to 945 MHz  
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a  
different crystal is required for each output frequency, the Si552 uses one  
fixed crystal frequency to provide a wide range of output frequencies. This  
IC-based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis  
provides superior supply noise rejection, simplifying the task of generating  
low-jitter clocks in noisy environments typically found in communication  
systems. The Si552 IC-based VCXO is factory-configurable for a wide  
variety of user specifications including frequency, supply voltage, output  
format, tuning slope, and temperature stability. Specific configurations are  
factory programmed at time of shipment, thereby eliminating the long lead  
times associated with custom oscillators.  
VC  
VDD  
1
2
3
6
5
4
FS  
CLK–  
CLK+  
GND  
Functional Block Diagram  
VDD  
CLK-  
CLK+  
Any-rate  
10–1400 MHz  
DSPLL®  
Fixed  
Frequency XO  
Clock Synthesis  
ADC  
FS  
VC  
GND  
Rev. 1.1 4/13  
Copyright © 2013 by Silicon Laboratories  
Si552  

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