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552AD000012BG PDF预览

552AD000012BG

更新时间: 2024-11-12 14:25:55
品牌 Logo 应用领域
芯科 - SILICON 机械振荡器
页数 文件大小 规格书
80页 3734K
描述
LVPECL Output Clock Oscillator, 644.53125MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

552AD000012BG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.63Is Samacsys:N
其他特性:IT CAN ALSO OPERATE AT 622.08 MHZ最大控制电压:3.3 V
最小控制电压:最长下降时间:0.35 ns
频率调整-机械:NO频率偏移/牵引率:80 ppm
频率稳定性:50%JESD-609代码:e4
安装特点:SURFACE MOUNT标称工作频率:644.53125 MHz
最高工作温度:85 °C最低工作温度:-40 °C
振荡器类型:LVPECL物理尺寸:177.8mm x 127.0mm x 41.91mm
最长上升时间:0.35 ns最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES最大对称度:55/45 %
端子面层:Nickel/Gold (Ni/Au)Base Number Matches:1

552AD000012BG 数据手册

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Si552  
DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)  
Features  
Available with any-rate output  
frequencies from 10–945 MHz and  
select frequencies to 1.4 GHz  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
Two selectable output frequencies Available CMOS, LVPECL, LVDS  
®
& CML outputs  
3rd generation DSPLL with superior  
jitter performance  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
3x better frequency stability than  
SAW-based oscillators  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 7.  
SONET/SDH  
xDSL  
10 GbE LAN / WAN  
Low-jitter clock generation  
Optical Modules  
Clock and data recovery  
Pin Assignments:  
See page 6.  
Description  
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced  
DSPLL circuitry to provide a very low jitter clock for all output frequencies.  
(Top View)  
®
The Si552 is available with any-rate output frequency from 10 to 945 MHz  
and select frequencies to 1400 MHz. Unlike traditional VCXO’s where a  
different crystal is required for each output frequency, the Si552 uses one  
fixed crystal frequency to provide a wide range of output frequencies. This  
IC based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis  
provides superior supply noise rejection, simplifying the task of generating  
low jitter clocks in noisy environments typically found in communication  
systems. The Si552 IC based VCXO is factory configurable for a wide  
variety of user specifications including frequency, supply voltage, output  
format, tuning slope, and temperature stability. Specific configurations are  
factory programmed at time of shipment, thereby eliminating long lead times  
associated with custom oscillators.  
VC  
VDD  
1
2
3
6
5
4
FS  
CLK–  
CLK+  
GND  
Functional Block Diagram  
VDD  
CLK-  
CLK+  
Any-rate  
10–1400 MHz  
DSPLL®  
Fixed  
Frequency XO  
Clock Synthesis  
ADC  
FS  
VC  
GND  
Rev. 0.5 7/06  
Copyright © 2006 by Silicon Laboratories  
Si552  

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