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552AC000009DG PDF预览

552AC000009DG

更新时间: 2024-11-07 18:12:27
品牌 Logo 应用领域
芯科 - SILICON 机械输出元件振荡器
页数 文件大小 规格书
15页 481K
描述
LVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, 74.175824MHz Nom, ROHS COMPLIANT PACKAGE-6

552AC000009DG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:ROHS COMPLIANT PACKAGE-6Reach Compliance Code:compliant
风险等级:5.63其他特性:COMPLEMENTARY OUTPUT; TRAY; 74.25 MHZ FREQUENCY ALSO AVAILABLE
最大控制电压:3.3 V最小控制电压:
最长下降时间:0.35 ns频率调整-机械:NO
频率偏移/牵引率:150 ppm频率稳定性:50%
线性度:10%安装特点:SURFACE MOUNT
端子数量:6最大工作频率:945 MHz
最小工作频率:10 MHz标称工作频率:74.175824 MHz
最高工作温度:85 °C最低工作温度:-40 °C
振荡器类型:LVPECL输出负载:50 OHM
封装主体材料:PLASTIC/EPOXY封装等效代码:DILCC6,.2
物理尺寸:7.0mm x 5.0mm x 1.8mm电源:3.3 V
认证状态:Not Qualified最长上升时间:0.35 ns
子类别:Other Oscillators最大压摆率:130 mA
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
最大对称度:55/45 %Base Number Matches:1

552AC000009DG 数据手册

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Si552  
REVISION D  
DUAL FREQUENCY VOLTAGE-CONTROLLED CRYSTAL  
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ  
Features  
Available with any-rate output  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
frequencies from 10–945 MHz and  
selected frequencies to 1.4 GHz  
Two selectable output frequencies  
®
3rd generation DSPLL with superior  
jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 10.  
SONET/SDH  
xDSL  
10 GbE LAN/WAN  
Low-jitter clock generation  
Optical modules  
Clock and data recovery  
Pin Assignments:  
See page 9.  
Description  
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced  
DSPLL circuitry to provide a very low jitter clock for all output frequencies.  
(Top View)  
®
The Si552 is available with any-rate output frequency from 10 to 945 MHz  
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a  
different crystal is required for each output frequency, the Si552 uses one  
fixed crystal frequency to provide a wide range of output frequencies. This  
IC-based approach allows the crystal resonator to provide exceptional  
frequency stability and reliability. In addition, DSPLL clock synthesis  
provides superior supply noise rejection, simplifying the task of generating  
low-jitter clocks in noisy environments typically found in communication  
systems. The Si552 IC-based VCXO is factory-configurable for a wide  
variety of user specifications including frequency, supply voltage, output  
format, tuning slope, and temperature stability. Specific configurations are  
factory programmed at time of shipment, thereby eliminating the long lead  
times associated with custom oscillators.  
VC  
VDD  
1
2
3
6
5
4
FS  
CLK–  
CLK+  
GND  
Functional Block Diagram  
VDD  
CLK-  
CLK+  
Any-rate  
10–1400 MHz  
DSPLL®  
Fixed  
Frequency XO  
Clock Synthesis  
ADC  
FS  
VC  
GND  
Rev. 1.2 6/18  
Copyright © 2018 by Silicon Laboratories  
Si552  

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