Datasheet > 550AM1134M000DGR

550AM1134M000DGR

更新时间： 2024-11-03 08:01:59

品牌	Logo	应用领域
芯科 - SILICON		石英晶振压控振荡器
页数	文件大小	规格书
14页	231K
描述
VCXO, Clock, 10MHz Min, 1417MHz Max, 1134MHz Nom

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550AM1134M000DGR 数据手册

Si550

REVISION D

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features

ꢀ

Available with any-rate output ꢀ Internal fixed crystal frequency

Si5602

frequencies from 10 to 945 MHz

and selected frequencies to

1.4 GHz

ensures high reliability and low

aging

ꢀ

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

ꢀ

3rd generation DSPLL with

ꢀ

superior jitter performance

3x better frequency stability than

SAW-based oscillators

ꢀ

Lead-free/RoHS-compliant

Ordering Information:

Applications

See page 8.

ꢀ

SONET/SDH

xDSL

10 GbE LAN/WAN

ꢀ

Low-jitter clock generation

Optical modules

Clock and data recovery

ꢀ

Pin Assignments:

See page 7.

Description

(Top View)

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXOs, where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC-based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory-configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating the long lead times associated with custom oscillators.

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

CLK– CLK+

V_DD

Any-rate

10-1400 MHz

DSPLL^®

Fixed

Frequency

Clock Synthesis

ADC

GND

Rev. 0.6 6/07

Si550

12 3 4 5 6 7...14

中文翻译

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与550AM1134M000DGR相关器件

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550AM156M250DG	SILICON	获取价格	LVPECL Output Clock Oscillator, 10MHz Min, 1417MHz Max, 156.25MHz Nom, ROHS COMPLIANT PACK
550AM156M250DGR	SILICON	获取价格	LVPECL Output Clock Oscillator, 10MHz Min, 1417MHz Max, 156.25MHz Nom, ROHS COMPLIANT PACK
550AM173M371DG	SILICON	获取价格	LVPECL Output Clock Oscillator, 10MHz Min, 1417MHz Max, 173.371MHz Nom, ROHS COMPLIANT PAC
550AM173M371DGR	SILICON	获取价格	LVPECL Output Clock Oscillator, 10MHz Min, 1417MHz Max, 173.371MHz Nom, ROHS COMPLIANT PAC
550AM595M350DG	SILICON	获取价格	LVPECL Output Clock Oscillator, 10MHz Min, 1417MHz Max, 595.35MHz Nom, ROHS COMPLIANT PACK
550AM85M1200DGR	SILICON	获取价格	LVPECL Output Clock Oscillator, 10MHz Min, 1417MHz Max, 85.12MHz Nom, ROHS COMPLIANT PACKA
550BA10M000DG	SILICON	获取价格	VCXO, Clock, 10MHz Min, 1417MHz Max, 10MHz Nom
550BA10M000DGR	SILICON	获取价格	VCXO, Clock, 10MHz Min, 1417MHz Max, 10MHz Nom
550BA1134M000DG	SILICON	获取价格	VCXO, Clock, 10MHz Min, 1417MHz Max, 1134MHz Nom
550BA1134M000DGR	SILICON	获取价格	VCXO, Clock, 10MHz Min, 1417MHz Max, 1134MHz Nom

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