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550AA010M000DGR PDF预览

550AA010M000DGR

更新时间: 2024-11-25 08:45:47
品牌 Logo 应用领域
芯科 - SILICON 机械输出元件振荡器
页数 文件大小 规格书
15页 108K
描述
LVPECL Output Clock Oscillator, 10MHz Nom,

550AA010M000DGR 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.62其他特性:TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR
最大控制电压:3.3 V最小控制电压:
最长下降时间:0.35 ns频率调整-机械:NO
频率偏移/牵引率:100 ppm频率稳定性:100%
线性度:10%安装特点:SURFACE MOUNT
标称工作频率:10 MHz最高工作温度:85 °C
最低工作温度:-40 °C振荡器类型:LVPECL
输出负载:50 OHM物理尺寸:7.0mm x 5.0mm x 1.8mm
最长上升时间:0.35 ns最大供电电压:3.63 V
最小供电电压:2.97 V标称供电电压:3.3 V
表面贴装:YES最大对称度:55/45 %
Base Number Matches:1

550AA010M000DGR 数据手册

 浏览型号550AA010M000DGR的Datasheet PDF文件第2页浏览型号550AA010M000DGR的Datasheet PDF文件第3页浏览型号550AA010M000DGR的Datasheet PDF文件第4页浏览型号550AA010M000DGR的Datasheet PDF文件第5页浏览型号550AA010M000DGR的Datasheet PDF文件第6页浏览型号550AA010M000DGR的Datasheet PDF文件第7页 
Si550  
REVISION D  
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)  
10 MHZ TO 1.4 GHZ  
Features  
Available with any frequency from  
10 to 945 MHz and select  
frequencies to 1.4 GHz  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
Si5602  
®
3rd generation DSPLL with  
superior jitter performance (0.5 ps)  
3x better temperature stability than  
SAW-based oscillators  
Excellent PSRR performance  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 10.  
SONET/SDH  
xDSL  
10 GbE LAN/WAN  
Low-jitter clock generation  
Optical modules  
Clock and data recovery  
Pin Assignments:  
See page 9.  
Description  
(Top View)  
®
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to  
provide a low-jitter clock at high frequencies. The Si550 supports any  
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike  
traditional VCXOs, where a different crystal is required for each output  
frequency, the Si550 uses one fixed crystal to provide a wide range of output  
frequencies. This IC-based approach allows the crystal resonator to provide  
exceptional frequency stability and reliability. In addition, DSPLL clock  
synthesis provides superior supply noise rejection, simplifying the task of  
generating low-jitter clocks in noisy environments typically found in  
communication systems. The Si550 IC-based VCXO is factory-configurable  
for a wide variety of user specifications, including frequency, supply voltage,  
output format, tuning slope, and temperature stability. Specific configurations  
are factory programmed at time of shipment, thereby eliminating the long  
lead times associated with custom oscillators.  
VC  
VDD  
1
2
3
6
5
4
OE  
CLK–  
CLK+  
GND  
Functional Block Diagram  
VDD  
Any-Frequency  
Fixed  
Frequency  
XO  
10 MHz–1.4 GHz  
CLK+  
CLK–  
DSPLL®  
Clock Synthesis  
ADC  
Vc  
OE  
GND  
Rev. 1.1 4/13  
Copyright © 2013 by Silicon Laboratories  
Si550  

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