January 1995
54F/74F378
Parallel D Register with Enable
General Description
The ’F378 is a 6-bit register with a buffered common En-
able. This device is similar to the ’F174, but with common
Enable rather than common Master Reset.
Features
Y
Y
Y
Y
Y
6-bit high-speed parallel register
Positive edge-triggered D-type inputs
Fully buffered common clock and enable inputs
Input clamp diodes limit high-speed termination effects
Full TTL and CMOS compatible
Package
Commercial
74F378PC
Military
Package Description
Number
N16E
J16A
16-Lead (0.300 Wide) Molded Dual-In-Line
×
54F378DM (QB)
16-Lead Ceramic Dual-In-Line
74F378SC (Note 1)
74F378SJ (Note 1)
M16A
M16D
W16A
E20A
16-Lead (0.150 Wide) Molded Small Outline, JEDEC
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
54F378FM (QB)
54F378LM (QB)
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
e
Note 1: Devices also available in 13 reel. Use suffix
×
SCX and SJX.
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9526–1
IEEE/IEC
TL/F/9526–2
TL/F/9526–3
TL/F/9526–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9526
RRD-B30M75/Printed in U. S. A.