Datasheet > 54F273LMB

54F273LMB

更新时间： 2024-11-26 05:32:23

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
8页	167K
描述
D FLIP-FLOP

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中文翻译

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数据手册

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54F273LMB 数据手册

May 1995

54F/74F273

Octal D Flip-Flop

General Description

Features

Ideal buffer for MOS microprocessor or memory

Eight edge-triggered D flip-flops

The ’F273 has eight edge-triggered D-type flip-flops with in-

dividual D inputs and Q outputs. The common buffered

Clock (CP) and Master Reset (MR) inputs load and reset

(clear) all flip-flops simultaneously.

Buffered common clock

Buffered, asynchronous Master Reset

See ’F377 for clock enable version

See ’F373 for transparent latch version

The register is fully edge-triggered. The state of each D in-

put, one setup time before the LOW-to-HIGH clock tran-

sition, is transferred to the corresponding flip-flop’s Q out-

put.

See ’F374 for TRI-STATE version

Guaranteed 4000V minimum ESD protection

All outputs will be forced LOW independently of Clock or

Data inputs by a LOW voltage level on the MR input. The

device is useful for applications where the true output only is

required and the Clock and Master Reset are common to all

storage elements.

Package

Commercial

74F273PC

Military

Package Description

Number

N20A

J20A

20-Lead (0.300 Wide) Molded Dual-In-Line

54F273DM (Note 2)

20-Lead Ceramic Dual-In-Line

74F273SC (Note 1)

74F273SJ (Note 1)

M20B

M20D

W20A

E20A

20-Lead (0.300 Wide) Molded Small Outline, JEDEC

20-Lead (0.300 Wide) Molded Small Outline, EIAJ

54F273FM (Note 2)

54F273LM (Note 2)

20-Lead Cerpack

20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13 reel. Use suffix

SCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

DMQB, FMQB and LMQB.

Logic Symbols

IEEE/IEC

TL/F/9511–3

TL/F/9511–5

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

1995 National Semiconductor Corporation

TL/F/9511

RRD-B30M75/Printed in U. S. A.

12 3 4 5 6 7 8

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