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54F280LM PDF预览

54F280LM

更新时间: 2024-02-13 01:06:13
品牌 Logo 应用领域
美国国家半导体 - NSC 逻辑集成电路
页数 文件大小 规格书
8页 155K
描述
9-Bit Parity Generator/Checker

54F280LM 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.21其他特性:ODD/EVEN PARITY GENERATOR
系列:F/FASTJESD-30 代码:R-GDIP-T14
逻辑集成电路类型:PARITY GENERATOR/CHECKER位数:9
功能数量:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):21 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

54F280LM 数据手册

 浏览型号54F280LM的Datasheet PDF文件第2页浏览型号54F280LM的Datasheet PDF文件第3页浏览型号54F280LM的Datasheet PDF文件第4页浏览型号54F280LM的Datasheet PDF文件第5页浏览型号54F280LM的Datasheet PDF文件第6页浏览型号54F280LM的Datasheet PDF文件第7页 
August 1995  
54F/74F280  
9-Bit Parity Generator/Checker  
General Description  
Features  
Y
Guaranteed 4000V minimum ESD protection  
The ’F280 is a high-speed parity generator/checker that ac-  
cepts nine bits of input data and detects whether an even or  
an odd number of these inputs is HIGH. If an even number  
of inputs is HIGH, the Sum Even output is HIGH. If an odd  
number is HIGH, the Sum Even output is LOW. The Sum  
Odd output is the complement of the Sum Even output.  
Package  
Commercial  
74F280PC  
Military  
Package Description  
Number  
N14A  
J14A  
14-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F280DM (Note 2)  
14-Lead Ceramic Dual-In-Line  
74F280SC (Note 1)  
74F280SJ (Note 1)  
M14A  
M14D  
W14B  
E20A  
14-Lead (0.150 Wide) Molded Small Outline, JEDEC  
×
14-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F280FM (Note 2)  
54F280LM (Note 2)  
14-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX and SJX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Logic Symbols  
Connection Diagrams  
Pin Assignment for  
DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
TL/F/9512–3  
IEEE/IEC  
TL/F/9512–1  
TL/F/9512–2  
TL/F/9512–5  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9512  
RRD-B30M115/Printed in U. S. A.  

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