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54ACT373DM PDF预览

54ACT373DM

更新时间: 2024-11-15 14:13:47
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
10页 166K
描述
ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20

54ACT373DM 技术参数

生命周期:Transferred包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57系列:ACT
JESD-30 代码:R-GDIP-T20长度:24.51 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):12.5 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

54ACT373DM 数据手册

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August 1998  
54AC373 54ACT373  
Octal Transparent Latch with TRI-STATE® Outputs  
General Description  
Features  
n ICC and IOZ reduced by 50%  
n Eight latches in a single package  
n TRI-STATE outputs for bus interfacing  
n Outputs source/sink 24 mA  
The ’AC/’ACT373 consists of eight latches with TRI-STATE  
outputs for bus organized system applications. The flip-flops  
appear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup time  
is latched. Data appears on the bus when the Output Enable  
(OE) is LOW. When OE is HIGH, the bus output is in the high  
impedance state.  
n ’ACT373 has TTL-compatible inputs  
n Standard Microcircuit Drawing (SMD)  
— ’AC373: 5962-87555  
— ’ACT373: 5962-87556  
Logic Symbols  
IEEE/IEC  
DS100329-1  
DS100329-2  
Pin Names  
Description  
Data Inputs  
Latch Enable Input  
D0–D7  
LE  
OE  
Output Enable Input  
O0–O7  
TRI-STATE Latch Outputs  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100329  
www.national.com  

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