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534AB000028BGR PDF预览

534AB000028BGR

更新时间: 2024-11-08 08:48:35
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
43页 2830K
描述
LVPECL Output Clock Oscillator, 166.62857MHz Nom, ROHS COMPLIANT, SMD, 8 PIN

534AB000028BGR 数据手册

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Si534  
QUAD FREQUENCY CRYSTAL OSCILLATOR (XO)  
(10 MHZ TO 1.4 GHZ)  
Features  
Available with any-rate output  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
frequencies from 10 MHz to 945 MHz  
and select frequencies to 1.4 GHz  
Four selectable output frequencies Available CMOS, LVPECL,  
®
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
3rd generation DSPLL with superior  
jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 7.  
SONET/SDH  
Networking  
SD/HD video  
Test and measurement  
Clock and data recovery  
FPGA/ASIC clock generation  
Pin Assignments:  
See page 6.  
Description  
(Top View)  
The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced  
DSPLL circuitry to provide a low jitter clock at high frequencies. The Si534  
FS[1]  
7
®
is available with any-rate output frequency from 10 to 945 MHz and select  
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is  
required for each output frequency, the Si534 uses one fixed crystal to  
provide a wide range of output frequencies. This IC based approach allows  
the crystal resonator to provide exceptional frequency stability and reliability.  
In addition, DSPLL clock synthesis provides superior supply noise rejection,  
simplifying the task of generating low jitter clocks in noisy environments  
typically found in communication systems. The Si534 IC-based XO is factory  
configurable for a wide variety of user specifications including frequency,  
supply voltage, output format, and temperature stability. Specific  
configurations are factory programmed at time of shipment, thereby  
eliminating long lead times associated with custom oscillators.  
VDD  
1
2
3
6
5
4
NC  
OE  
CLK–  
CLK+  
GND  
8
FS[0]  
(LVDS/LVPECL/CML)  
FS[1]  
7
Functional Block Diagram  
VDD  
1
2
3
6
5
4
NC  
OE  
VDD  
CLK– CLK+  
NC  
GND  
CLK  
Any-rate  
10–1400 MHz  
DSPLL®  
8
Fixed  
FS[1]  
Frequency  
XO  
FS[0]  
FS[0]  
Clock  
(CMOS)  
Synthesis  
OE  
GND  
Rev. 1.0 7/06  
Copyright © 2006 by Silicon Laboratories  
Si534  

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