Datasheet > 533JC160M000DG

533JC160M000DG

更新时间： 2024-09-20 06:11:07

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
12页	225K
描述
Oscillator

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533JC160M000DG 数据手册

Si533

REVISION D

DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 1.4 GHZ)

Features

ꢀ

Available with any-rate output

ꢀ

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Si5602

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

2 selectable output frequencies

ꢀ

3rd generation DSPLL with superior

ꢀ

jitter performance

ꢀ

3x better frequency stability than

SAW-based oscillators

Pin 1 output enable (OE)

ꢀ

Pb-free/RoHS-compliant

Applications

Ordering Information:

See page 7.

ꢀ

SONET/SDH

Networking

SD/HD video

ꢀ

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

Description

The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL circuitry to provide a low jitter clock at high frequencies. The Si533

(Top View)

is available with any-rate output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is

required for each output frequency, the Si533 uses one fixed crystal to

provide a wide range of output frequencies. This IC based approach allows

the crystal resonator to provide exceptional frequency stability and reliability.

In addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low jitter clocks in noisy environments

typically found in communication systems. The Si533 IC based XO is factory

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, and temperature stability. Specific

configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

V_DD

CLK–

CLK+

GND

LVDS/LVPECL/CML

Functional Block Diagram

V_DD

CLK– CLK+

Any-rate

10–1400 MHz

DSPLL®

Clock

Synthesis

GND

CLK+

Fixed

Frequency

CMOS

GND

Rev. 1.1 6/07

Si533

12 3 4 5 6 7...12

中文翻译

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