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530AB622M080BGR PDF预览

530AB622M080BGR

更新时间: 2024-10-28 03:02:59
品牌 Logo 应用领域
芯科 - SILICON 振荡器晶体振荡器石英晶振机械
页数 文件大小 规格书
10页 184K
描述
CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

530AB622M080BGR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.57最长下降时间:0.35 ns
频率调整-机械:NO频率稳定性:20%
JESD-609代码:e4安装特点:SURFACE MOUNT
标称工作频率:622.08 MHz最高工作温度:85 °C
最低工作温度:-40 °C振荡器类型:LVPECL
物理尺寸:177.8mm x 127.0mm x 41.91mm最长上升时间:0.35 ns
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V表面贴装:YES
最大对称度:55/45 %端子面层:Nickel/Gold (Ni/Au)
Base Number Matches:1

530AB622M080BGR 数据手册

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Si530/531  
Table 3. CLK± Output Levels and Symmetry  
Parameter  
Symbol  
Test Condition  
mid-level  
Min  
VDD – 1.42  
1.1  
Typ  
Max  
VDD – 1.25  
1.9  
Units  
V
1
LVPECL Output Option  
V
O
VOD  
VSE  
swing (diff)  
VPP  
VPP  
V
swing (single-ended)  
mid-level  
0.5  
0.93  
1.275  
0.50  
2
LVDS Output Option  
V
1.125  
0.32  
1.20  
0.40  
O
swing (diff)  
VOD  
VO  
VPP  
V
2
CML Output Option  
mid-level  
V
– 0.75  
DD  
VOD  
VOH  
VOL  
swing (diff)  
0.70  
0.8 x VDD  
0.95  
1.20  
VDD  
VPP  
3
CMOS Output Option  
I
= 32 mA  
OH  
V
IOL = 32 mA  
0.4  
Rise/Fall time (20/80%)  
Symmetry (duty cycle)  
tR, F  
t
LVPECL/LVDS/CML  
CMOS with CL = 15 pF  
350  
ps  
ns  
1
SYM  
LVPECL:  
LVDS:  
V
– 1.3 V (diff)  
DD  
45  
55  
%
1.25 V (diff)  
/2  
CMOS:  
V
DD  
Notes:  
1. 50 to VDD – 2.0 V.  
2. Rterm = 100 (differential).  
3. CL = 15 pF  
Table 4. CLK± Output Phase Jitter  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Phase Jitter (RMS)*  
φJ  
φJ  
12 kHz to 20 MHz (OC-48)  
50 kHz to 80 MHz (OC-192)  
0.27  
0.30  
ps  
for F  
> 500 MHz  
OUT  
Phase Jitter (RMS)*  
for F of 125 to 500 MHz  
12 kHz to 20 MHz (OC-48)  
0.50  
ps  
OUT  
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.  
Table 5. CLK± Output Period Jitter  
Parameter  
Period Jitter*  
Symbol  
Test Condition  
RMS  
Min  
Typ  
1
Max  
Units  
J
ps  
PER  
for F < 160 MHz  
OUT  
Peak-to-Peak  
5
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.  
Preliminary Rev. 0.4  
3

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