Datasheet > 530AA26M0000BG

530AA26M0000BG

更新时间： 2024-11-06 07:25:27

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
15页	265K
描述
LVPECL Output Clock Oscillator, 26MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530AA26M0000BG 数据手册

Si530/531

CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 1.4 GHZ)

Features

Si5602

ꢀ

Available with any-rate output

ꢀ

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

ꢀ

3rd generation DSPLL with superior

jitter performance

ꢀ

3x better frequency stability than

SAW-based oscillators

ꢀ

Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 7.

ꢀ

SONET/SDH

Networking

SD/HD video

ꢀ

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

Description

(Top View)

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

V_DD

CLK–

CLK+

GND

Si530 (LVDS/LVPECL/CML)

V_DD

Functional Block Diagram

GND

CLK

V_DD

CLK– CLK+

Si530 (CMOS)

V_DD

Any-rate

10–1400 MHz

DSPLL^®

Clock

Synthesis

Fixed

Frequency

CLK–

CLK+

GND

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

12 3 4 5 6 7...15

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