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530AA1003M00DG PDF预览

530AA1003M00DG

更新时间： 2024-11-13 06:25:51
品牌 Logo 应用领域
芯科 - SILICON 机械振荡器
页数 文件大小 规格书
12页 111K
描述
LVPECL Output Clock Oscillator, 1003MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530AA1003M00DG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code：unknown风险等级：5.57
其他特性：TRAY最长下降时间：0.35 ns
频率调整-机械：NO频率稳定性：50%
JESD-609代码：e4安装特点：SURFACE MOUNT
标称工作频率：1003 MHz最高工作温度：85 °C
最低工作温度：-40 °C振荡器类型：LVPECL
物理尺寸：7.0mm x 5.0mm x 1.85mm最长上升时间：0.35 ns
最大供电电压：3.63 V最小供电电压：2.97 V
标称供电电压：3.3 V表面贴装：YES
最大对称度：55/45 %端子面层：Nickel/Gold (Ni/Au)
Base Number Matches：1

530AA1003M00DG 数据手册

 浏览型号530AA1003M00DG的Datasheet PDF文件第2页浏览型号530AA1003M00DG的Datasheet PDF文件第3页浏览型号530AA1003M00DG的Datasheet PDF文件第4页浏览型号530AA1003M00DG的Datasheet PDF文件第5页浏览型号530AA1003M00DG的Datasheet PDF文件第6页浏览型号530AA1003M00DG的Datasheet PDF文件第7页 
Si530/531  
REVISION D  
CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)  
Features  
Si5602  
Available with any-rate output  
Internal fixed crystal frequency  
ensures high reliability and low  
aging  
Available CMOS, LVPECL,  
LVDS, and CML outputs  
3.3, 2.5, and 1.8 V supply options  
Industry-standard 5 x 7 mm  
package and pinout  
frequencies from 10 MHz to 945 MHz  
and select frequencies to 1.4 GHz  
®
3rd generation DSPLL with superior  
jitter performance  
3x better frequency stability than  
SAW-based oscillators  
Pb-free/RoHS-compliant  
Ordering Information:  
Applications  
See page 7.  
SONET/SDH  
Networking  
SD/HD video  
Test and measurement  
Clock and data recovery  
FPGA/ASIC clock generation  
Pin Assignments:  
See page 6.  
Description  
(Top View)  
®
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry  
to provide a low jitter clock at high frequencies. The Si530/531 is available  
with any-rate output frequency from 10 to 945 MHz and select frequencies to  
1400 MHz. Unlike a traditional XO, where a different crystal is required for  
each output frequency, the Si530/531 uses one fixed crystal to provide a  
wide range of output frequencies. This IC based approach allows the crystal  
resonator to provide exceptional frequency stability and reliability. In addition,  
DSPLL clock synthesis provides superior supply noise rejection, simplifying  
the task of generating low jitter clocks in noisy environments typically found in  
communication systems. The Si530/531 IC based XO is factory configurable  
for a wide variety of user specifications including frequency, supply voltage,  
output format, and temperature stability. Specific configurations are factory  
programmed at time of shipment, thereby eliminating long lead times  
associated with custom oscillators.  
VDD  
1
2
3
6
5
4
NC  
OE  
CLK–  
CLK+  
GND  
Si530 (LVDS/LVPECL/CML)  
VDD  
1
2
3
6
5
4
OE  
NC  
NC  
Functional Block Diagram  
GND  
CLK  
VDD  
CLK– CLK+  
Si530 (CMOS)  
VDD  
1
2
3
6
5
4
OE  
NC  
Any-rate  
10–1400 MHz  
DSPLL®  
Clock  
Synthesis  
Fixed  
Frequency  
XO  
CLK–  
CLK+  
GND  
Si531 (LVDS/LVPECL/CML)  
OE  
GND  
Rev. 1.2 5/11  
Copyright © 2011 by Silicon Laboratories  
Si530/531  
1234567...12

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