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500DRAD0M90000ACFR PDF预览

500DRAD0M90000ACFR

更新时间: 2024-11-24 20:54:19
品牌 Logo 应用领域
芯科 - SILICON 石英晶振
页数 文件大小 规格书
6页 71K
描述
XO, Clock, 0.9MHz Min, 200MHz Max, 0.9MHz Nom

500DRAD0M90000ACFR 技术参数

是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.71
安装特点:SURFACE MOUNT端子数量:6
最大工作频率:200 MHz最小工作频率:0.9 MHz
标称工作频率:0.9 MHz最高工作温度:70 °C
最低工作温度:最大输出低电流:9 mA
封装主体材料:PLASTIC/EPOXY封装等效代码:SOLCC6,.12
电源:2.5 V认证状态:Not Qualified
子类别:Other Oscillators标称供电电压:2.5 V
表面贴装:YESBase Number Matches:1

500DRAD0M90000ACFR 数据手册

 浏览型号500DRAD0M90000ACFR的Datasheet PDF文件第2页浏览型号500DRAD0M90000ACFR的Datasheet PDF文件第3页浏览型号500DRAD0M90000ACFR的Datasheet PDF文件第4页浏览型号500DRAD0M90000ACFR的Datasheet PDF文件第5页浏览型号500DRAD0M90000ACFR的Datasheet PDF文件第6页 
Si500D  
DIFFERENTIAL OUTPUT SILICON OSCILLATOR  
Features  
Quartz-free, MEMS-free, and PLL-free all-silicon  
oscillator  
Any-rate output frequencies from 0.9 to 200 MHz  
Short lead times  
Excellent temperature stability (±20 ppm)  
Highly reliable startup and operation  
High immunity to shock and vibration  
Low jitter: <1.5 ps  
0 to 85 °C operation includes 10-year aging in hot  
environments  
Footprint compatible with industry-  
standard 3.2 x 5.0 mm XOs  
CMOS and SSTL versions available  
Driver stopped, tri-state, or powerdown  
operation  
RoHS compliant  
1.8, 2.5, or 3.3 V options  
Low power  
More than 10x better fit rate than  
competing crystal solutions  
Specifications  
Parameters  
Condition  
Min  
Typ  
Max  
Units  
Frequency Range  
0.9  
200  
MHz  
Temperature stability,  
0 to +70 °C  
±10  
ppm  
ppm  
ppm  
ppm  
Temperature stability,  
0 to +85 °C  
±20  
Frequency Stability  
Total stability,  
±150  
±250  
0 to +70 °C operation1  
Total stability,  
0 to +85 °C operation2  
Operating Temperature  
Storage Temperature  
0
+85  
+125  
1.98  
2.75  
3.63  
36.0  
22.2  
16.5  
29.3  
C°  
C°  
V
–55  
1.71  
2.25  
2.97  
1.8 V option  
2.5 V option  
3.3 V option  
LVPECL  
Supply Voltage  
V
V
34.0  
19.3  
14.9  
25.3  
mA  
mA  
mA  
mA  
Low Power LVPECL  
LVDS  
HCSL  
Differential CMOS(3.3 V  
option,10 pF,200 MHz)  
29.0  
31.8  
mA  
Supply Current  
Differential SSTL-3  
Differential SSTL-2  
Differential SSTL-18  
Tri-State  
24.5  
24.3  
22.2  
9.7  
27.7  
mA  
mA  
mA  
mA  
mA  
%
26.7  
25  
10.7  
Powerdown  
1.0  
1.9  
Output Symmetry  
VDIFF = 0  
46 – 13 ns/TCLK  
54 + 13 ns/TCLK  
Notes:  
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,  
first-year aging at 25 °C, shock, vibration, and one solder reflow.  
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,  
ten-year aging at 85 °C, shock, vibration, and one solder reflow.  
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding  
output clock termination recommendations.  
4. Min column entries are minima of VOH. Max column entries are maxima of VOL.  
Rev. 0.3 5/09  
Copyright © 2009 by Silicon Laboratories  
Si500D  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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