Datasheet > 500DUAF200M000ABFR

500DUAF200M000ABFR

更新时间： 2024-11-25 10:41:31

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
4页	91K
描述
Oscillator, 0.9MHz Min, 200MHz Max, 200MHz Nom

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Si500D

DIFFERENTIAL OUTPUT SILICON OSCILLATOR

Features

Quartz-free silicon oscillator

Any-rate output frequencies from 0.9 to 200 MHz

Quick turn delivery

Highly reliable startup and operation

Tri-state or power down operation

1.8, 2.5, or 3.3 V options

LVPECL, LVDS, HCSL, differential CMOS,

and differential SSTL versions available

3.2 x 4.0 mm footprint compatible with

industry-standard 3.2 x 5.0 mm pinout

Low power

Pb-free and RoHS compliant

Specifications

Parameters

Condition

Min

Typ

Max

Units

Frequency Range

0.9

—

–55

1.71

2.25

2.97

—

34.0

19.3

14.9

25.3

29.0

24.5

24.3

22.2

9.7

1.0

—

1.1

—

200

±150

+70

MHz

ppm

C°

Frequency Stability

Operating Temperature

Storage Temperature

See Note 1.

+125

1.98

2.75

3.63

36.0

22.2

16.5

29.3

31.8

27.7

26.7

1.8 V option

2.5 V option

3.3 V option

Supply Voltage

LVPECL

Low Power LVPECL

LVDS

HCSL

Differential CMOS(3.3 V option,10 pF,200 MHz)

Differential SSTL-3

Differential SSTL-2

Differential SSTL-18

Tri-State

Supply Current

10.7

1.9

54 + 13 ns/T

460

Powerdown

—

Output Symmetry

= 0

46 – 13 ns/T

DIFF

CLK

LVPECL/LVDS

HCSL/Differential SSTL

Differential CMOS, 15 pF, >80 MHz

Mid-level

—

800

1.6

– 1.34

.880

Rise and Fall Times (20/80%)

– 1.5

LVPECL Output Option

(DC coupling, 50 Ω to V – 2.0 V)

Diff swing

.720

Mid-level

Diff swing

Mid-level

Diff swing

Mid-level

Diff swing

Mid-level

Diff swing

—

.68

N/A

—

Low Power LVPECL Output Option

(AC coupling, 100 Ω Differential Load)

.95

1.26

0.45

0.96

0.45

.425

.82

1.15

0.25

0.85

0.25

0.35

0.65

LVDS Output Option (2.5/3.3 V)

= 100 Ω diff)

TERM

LVDS Output Option (1.8 V)

= 100 Ω diff)

TERM

HCSL Output Option

DC termination per pad

, sourcing 9 mA

– 0.6

—

0.6

CMOS Output Voltage

, sinking 9 mA

SSTL-18

SSTL-2

.5 x V + 0.375

.5 x V + 0.48

.5 x V – 0.375

.5 x V – 0.48

SSTL Output Voltage

SSTL-3

.45 x V + 0.48

—

.45 V – 0.48

Powerup Time

OE Deassertion to Clk Stop

Return from Output Driver Stopped Mode

Return From Tri-State Time

Return From Powerdown Time

From time V crosses min spec supply

—

µs

250 + 3 x T

12 + 3 x T

CLK

Non-CMOS

ps RMS

Period Jitter (1-sigma)

CMOS, C = 7 pF

1.0 MHz – min(20 MHz, 0.4 x F

),non-CMOS

0.6

0.7

OUT

Integrated Phase Jitter

1.0 MHz – min(20 MHz, 0.4 x F

),CMOS format

1.5

OUT

Notes:

1. Inclusive of 25 C° initial frequency accuracy, operating temperature range, supply voltage change, output load change, 1st year aging at

25 C°, shock and vibration.

2. See AN409 for further details regarding output clock termination recommendations. SSTL minimum output voltage is minimum V_OH. SSTL

maximum output voltage is maximum V_OL

Rev. 0.2 9/08

Si500D

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

12 3 4

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