Datasheet > 39K50

39K50

更新时间： 2022-11-24 21:47:48

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
86页	1209K
描述
CPLDs at FPGA DensitiesTM

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数据手册

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39K50 数据手册

Delta39K™ ISR™

CPLD Family

inputs are driven from

the routing channels

4096-bit Dual-Port

Array

Global Clock

Signals

Configurable as

Async/Sync Dual-Port

or Sync FIFO

GCLK[3:0]

Configurable as

4K x 1, 2K x 2, 1K x 4,

and 512 x 8 block sizes

All channel memory outputs

drive dedicated tracks in the

routing channels

Horizontal Channel

Figure 6. Block Diagram of Channel Memory Block

I/O Cell

I/O Banks

The Delta39K interfaces the horizontal and vertical routing

channels to the pins through I/O banks. There are eight I/O

banks per device as shown in Figure 7, and all I/Os from an

I/O bank are located in the same section of a package for PCB

layout convenience.

Figure 8 is a block diagram of the Delta39K I/O cell. The I/O

cell contains a three-state input buffer, an output buffer, and a

The output buffer has a slew rate control option that can be

used to configure the output for a slower slew rate. The input

of the device and the pin output can each be configured as

registered or combinatorial; however, only one path can be

configured as registered in a given design.

Delta39K devices support True Vertical Migration™ (i.e., for

each package type, Delta39K devices of different densities

keep given pins in the same I/O banks). This allows for easy

and simple implementation of multiple I/O standards during the

design and prototyping phase, before a final density has been

determined. Please refer to the application note titled “Family,

Package and Density Migration in Delta 39K and Quantum38K

CPLDs.”

The output enable in an I/O cell can be selected from one of

the four global control signals or from one of two Output

Control Channel (OCC) signals. The output enable can be

configured as always enabled or always disabled or it can be

controlled by one of the remaining inputs to the mux. The

selection is done via a mux that includes V_CCand GND as

inputs.

Each I/O bank contains several I/O cells, and each I/O cell

contains an input/output register, an output enable register,

programmable slew rate control and programmable bus hold

control logic. Each I/O cell drives a pin output of the device;

the cell also supplies an input to the device that connects to a

dedicated track in the associated routing channel.

bank 7

bank 6

Each I/O bank can use any supported I/O standard by

supplying appropriate V_REFand V_CCIOvoltages and config-

uring the I/O through the Warp software. All the V_REFand

V_CCIOpins in an I/O bank must be connected to the same V_REF

and V_CCIOvoltage respectively. This requirement restricts the

number of I/O standards supported by an I/O bank at any given

time.

Delta39K

The number of I/Os which can be used in each I/O bank

depend on the type of I/O standards and the number of V_CCIO

and GND pins being used. This restriction is derived from the

electromigration limit of the V_CCIOand GND bussing on the

chip. Please refer to the note on page 17 and the application

note titled “Delta39K Family Device I/O Standards and Config-

urations” for details.

bank 2

bank 3

Figure 7. Delta39K I/O Bank Block Diagram

Document #: 38-03039 Rev. *H

Page 9 of 86

1...6 7 8910 11 12...86

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