Datasheet > 39K50

39K50

更新时间： 2022-11-24 21:47:48

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
86页	1209K
描述
CPLDs at FPGA DensitiesTM

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39K50 数据手册

Delta39K™ ISR™

CPLD Family

Document History Page

Document Title: Delta39K™ ISR™ CPLD Family CPLDs at FPGA Densities™

Document Number: 38-03039

Issue

Date

Orig. of

Change

REV. ECN NO.

Description of Change

Change from Spec #: 38-00830 to 38-03039

106503

107625

05/30/01

07/11/01

SZV

Deleted 39K15 device and the associated -250-MHz bin specs

Deleted 144FBGA package and associated part numbers

Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A”

Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”

Changed the part ordering information accordingly

Updated the -233-MHz timing specs to match modified timing specs achieved by

design (main affected params: t_PD, t_MCCO, t_IOS, t_SCS, t_SCS2, f_MAX2, t_CLMAA

t_CLMCYC2, t_CHMCYC2, t_CHMCLK

)

Updated I/O standard Timing Delay Specs and changed the default I/O standard

from 3.3V PCI to LVCMOS

Added paragraph about Delta39K being CompactPCI hot swap Ready

Added X8 mode in the PLL description

Added Standby ICC spec

Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead

of CY3LV020

109681

11/16/01

Updated Delta39K family offering

Modified PLL timing parameters t_DWSA, t_DWOSA, t_MCCJ, andt_LOCK. Addedt_INDUTY

parameter

Deleted exception to CompactPCI Hot Swap compliance regarding “PCI

buffers....”

Added reference to app note “Hot Socketing Delta39K”

Revised CompactPCI Hot Swap Specification R1.0 to be R2.0

112376

112946

12/21/01

04/04/02

Combined with spec# 38-03040

Updated pin tables for 39K30 (208PQFP, 256FBGA)

Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA)

Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL

Added PLL parameters (f_PLLVCO, P_SAPLLI, f_MPPLI

)

Added and updated Storage Temperature for 39K200-208EQFP

Changed the I_cc0spec for 39K165 and 39K200

Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin

Updated Input and Output Standard Timing Delay Adjustment table

Removed Self Boot Industrial parts from the offering

Removed Delta39K165Z (1.8V) from the offering

Removed 144-FBGA package offering

Added self-boot Flash Memory endurance and data retention data

Added Family, Package, and Density Migration section

Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs

117518

10/04/02

OOR

Changed data sheet status from Preliminary to Final

Added note 7 to DC Characteristics

121063

122543

11/06/02

12/10/02

DSG

Updated spec 51-85103 (MG388 package drawing) to rev. *C

Changed the definition of following pins on CY39030 -256FBGA package:

Pin A10: From IO/Vref7 to IO/Vref6

Pin B7: From IO/Vref6 to V_CC

Added Table to identify Bank Location of Global Clock and Global Control Pins

128684

08/04/03

OOR

Removed all “Z” parts (1.8V)

Referenced EEPROM to ATMEL part number

Document #: 38-03039 Rev. *H

Page 86 of 86

1...83 84 8586

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