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360-170.000MHZ-BE0 PDF预览

360-170.000MHZ-BE0

更新时间: 2024-11-07 07:20:15
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2页 199K
描述
LVPECL Output Clock Oscillator, 170MHz Nom, ROHS COMPLIANT PACKAGE-6

360-170.000MHZ-BE0 数据手册

 浏览型号360-170.000MHZ-BE0的Datasheet PDF文件第2页 
lVE-PEcl 7x5mm 2.5V Osꢃiꢄꢄaꢅor  
RoHꢂ compꢄianꢅ / Pꢆ Free  
F4620 ꢂERꢁEꢂ  
Rev. 3/24/2009  
Page 1 of 2  
http://www.foxonline.com/need_a_sample.htm  
FEAtuREꢂ  
XpressO® Equivalent  
2.5V Operation  
LV-PECL Output  
• Complementary Outputs  
• Standby Function  
FXO-PC72  
Why XpressO?  
Lower Cost, Faster Delivery, Low Jitter!  
• Tape and Reel (2,000 pcs. STD)  
• PARt ꢀuMbER ꢂElEctꢁOLearn More - Internet Required  
Operating  
Frequency  
Range (MHz)  
Model Frequency  
Part Number  
Number Stability1 Temperature (ºC)  
359-Frequency-xxxxx  
729-Frequency-xxxxx  
360-Frequency-xxxxx  
730-Frequency-xxxxx  
720-Frequency-xxxxx  
731-Frequency-xxxxx  
-10 ~ +70  
-40 ~ +85  
-10 ~ +70  
-40 ~ +85  
-10 ~ +70  
-40 ~ +85  
40.000 ~ 280.000  
40.000 ~ 280.000  
40.000 ~ 280.000  
40.000 ~ 280.000  
40.000 ~ 280.000  
40.000 ~ 170.000  
F4620  
F4620R ±100PPM  
±100PPM  
F4625  
F4625R  
F4626  
±50PPM  
±50PPM  
±25PPM*  
F4626R ±25PPM*  
• ElEctRꢁcAl cHARActERꢁꢂtꢁcꢂ  
MAX (unless otherwise noted)  
PARAMETERS  
Frequency Range (Fo)  
Storage Temperature Range (Tstg)  
40.000 ~ 280.000 MHz  
-55ºC ~ +125ºC  
2.5V ± 5%  
Supply Voltage  
Input Current  
(Vdd)  
(Idd)  
88mA  
Output Symmetry (50% Vp-p Level)  
40.000 MHz ~ 170.000 MHz  
45% ~ 55%  
170.000* Mhz ~ 280.000 MHz  
Rise Time (Tr) (20% ~ 80% Vp-p)  
Fall Time (Tf)(80% ~ 20% Vp-p)  
40% ~ 60%  
1nS  
1nS  
Output Voltage  
(Vol)  
(Voh)  
1.195V  
1.415 V Min  
Standby Current  
Output Load  
30µA  
See Recommended Circuit  
Start-up Time  
(Ts)  
10mS  
200nS  
10mS  
Output Disable Time  
Output Enable Time  
Jitter  
12kHz ~ 20MHz  
RMS Period  
Cycle-to-Cycle  
0.3pS Typ.  
2.5pS Typ.  
20pS Typ.  
1 Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, aging,  
shock, and vibration. (*Excludes shock and vibration)  
2 An internal pullup resistor from pin 1 to pin 6 allows active output if pin 1 is left open.  
Note: A 0.01µF bypass capacitor should be placed between Vdd (Pin 6) and GND (Pin 3) to  
minimize power supply line noise.  
Drawing is for reference to critical specifications defined by size measurements.  
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may vary.  
All specifications subject to change without notice.  
All dimensions are in millimeters.  
• EꢀAblE / DꢁꢂAblE FuꢀctꢁOꢀ2  
OUTPUT (Pin 4)  
ACTIVE  
OUTPUT (Pin 5)  
ACTIVE  
(Pin 1)  
OPEN2  
ACTIVE  
High Z  
ACTIVE  
High Z  
'1' Level Vih 70% Vdd  
'0' Level Vil 30% Vdd  
FOXElectronics 5570 Enterprise Parkway Fort Myers, Florida 33905 USA +1.239.693.0099 FAX +1.239.693.1554 http://www.foxonline.com  
EMEA Tel/Fax: +44 .1767.312632 | Asia Hong Kong Tel: +852.2854.4285 Fax +852.2854.4282  
| Japan Tel: +81.3.3374/2079 Fax: +81.3.3374.5221  
© 2009 FOX ELECTRONICS | ISO9001:2000 Certified  

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