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34712

更新时间: 2024-02-17 08:46:21
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 开关双倍数据速率
页数 文件大小 规格书
23页 473K
描述
3.0A 1.0MHz Fully Integrated DDR Switch-Mode Power Supply

34712 数据手册

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FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
In modern microprocessor/memory applications, address  
commands and control lines require system level termination  
to a voltage (VTT) equal to 1/2 the memory supply voltage  
(VDDQ). Having the termination voltage at midpoint, the power  
supply insures symmetry for switching times. Also, a  
continuous current. It provides protection against output over  
current, overvoltage, undervoltage, and overtemperature  
conditions. It also protects the system from short circuit  
events. It incorporates a power-good output signal to alert the  
host when a fault occurs.  
reference voltage (VREF) that is free of any noise or voltage  
variations is needed for the DDR SDRAM input receiver,  
VREF is also equal to 1/2 VDDQ. Varying the VREF voltage will  
effect the setup and hold time of the memory. To comply with  
DDR requirements and to obtain best performance, VTT and  
VREF need to be tightly regulated to track 1/2 VDDQ across  
voltage, temperature, and noise margins. VTT should track  
any variations in the DC VREF value (VTT = VREF +/- 40 mV),  
(See Figure 4) for a DDR system level diagram.  
For boards that support the Suspend-To-RAM (S3) and  
the Suspend-To-Disk (S5) states, the 34712 offers the STBY  
and the SD pins respectively. Pulling any of these pins low,  
puts the IC in the corresponding state.  
By integrating the control/supervisory circuitry along with  
the Power MOSFET switches for the buck converter into a  
space-efficient package, the 34712 offers a complete, small-  
size, cost-effective, and simple solution to satisfy the needs  
of DDR memory applications.  
The 34712 supplies the VTT and a buffered VREF output.  
To ensure compliance with DDR specifications, the VDDQ line  
is applied to the VREFIN pin and divided by 2 internally  
through a precision resistor divider. This internal voltage is  
then used as the reference voltage for the VTT output. The  
same internal voltage is also buffered to give the VREF  
voltage at the VREFOUT pin for the application to use without  
the need for an external resistor divider. The 34712 provides  
the tight voltage regulation and power sequencing/tracking  
required along with handling the DDR peak transient current  
requirements. Buffering the VREF output helps its immunity  
against noise and load changes.  
Besides DDR memory termination, the 34712 can be used  
to supply termination for other active buses and graphics card  
memory. It can be used in Netcom/Telecom applications like  
servers. It can also be used in desktop motherboards, game  
consoles, set top boxes, and high end high definition TVs.  
V
V
V
DDQ  
DDQ  
TT  
R
T
R
S
The 34712 utilizes a voltage mode synchronous buck  
switching converter topology with integrated low RDS(ON)  
(45 m) N-channel power MOSFETs to provide a VTT voltage  
with an accuracy of less than ±2.0 %. It has a programmable  
switching frequency that allows for flexibility and optimization  
over the operating conditions and can operate at up to  
1.0 MHz to significantly reduce the external components size  
and cost. The 34712 can sink and source up to 3.0 A of  
V
REF  
BUS  
DDR Memory Input Receiver  
DDR Memory Controller  
Figure 4. DDR System Level Diagram  
FUNCTIONAL PIN DESCRIPTION  
REFERENCE VOLTAGE INPUT (VREFIN)  
FREQUENCY ADJUSTMENT INPUT (FREQ)  
The 34712 will track 1/2 the voltage applied at this pin.  
The buck converter switching frequency can be adjusted  
by connecting this pin to an external resistor divider between  
VDDI and GND pins. The default switching frequency (FREQ  
pin connected to ground, GND) is set at 1.0 MHz.  
REFERENCE VOLTAGE OUTPUT (VREFOUT)  
This is a buffered reference voltage output that is equal to  
1/2 VREFIN. It has a 10.0 mA current drive capability. This  
output is used as the VREF voltage rail and should be filtered  
against any noise. Connect a 0.1 µF, 6 V low ESR ceramic  
filter capacitor between this pin and the GND pin and  
between this pin and VDDQ rail. VREFOUT is also used as the  
reference voltage for the buck converter error amplifier.  
SIGNAL GROUND (GND)  
Analog ground of the IC. Internal analog signals are  
referenced to this pin voltage.  
34712  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
10  

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