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309RILFT PDF预览

309RILFT

更新时间: 2024-11-07 01:20:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟PC光电二极管外围集成电路晶体
页数 文件大小 规格书
10页 123K
描述
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH

309RILFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QSOP
包装说明:SSOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.71
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:8.65 mm湿度敏感等级:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:50 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

309RILFT 数据手册

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DATASHEET  
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH  
ICS309  
Description  
Features  
The ICS309 is a versatile serially-programmable, triple  
PLL with spread spectrum clock source. The ICS309  
can generate any frequency from 250kHz to 200 MHz,  
and up to 6 different output frequencies simultaneously.  
The outputs can be reprogrammed on-the-fly, and will  
lock to a new frequency in 10 ms or less.  
Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS  
compliant  
Highly accurate frequency generation  
M/N Multiplier PLL: M = 1..2048, N = 1..1024  
Serially programmable: user determines the output  
frequency via a 3-wire interface  
To reduce system EMI emissions, spread spectrum is  
available that supports modulation frequencies of  
31 kHz and 120 kHz, as well as modulation amplitudes  
of +/-0.25% to +/-2.0%. Both center and down-spread  
options are available.  
Spread Spectrum frequency modulation for reduced  
system EMI  
Center or Down Spread up to 4% total  
Selectable 32 kHz and 120 kHz modulation  
Eliminates need for custom quartz oscillators  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 3 - 50 MHz  
Output clock frequencies up to 200 MHz  
Operating voltage of 3.3 V  
The device includes a PDTS pin which tri-states the  
output clocks and powers down the entire chip.  
The ICS309 default for non-programmed start-up are  
buffered reference clock outputs on all clock output  
pins.  
TM  
IDT’s VersaClock programming software allows the  
user to configure up to 9 outputs with target  
Up to 9 reference clock outputs  
Power down tri-state mode  
frequencies, spread spectrum capabilities or buffered  
TM  
reference clock outputs. The VersaClock software  
automatically configures the PLLs for optimal overall  
performance.  
Very low jitter  
Block Diagram  
3
VDD  
PLL1 with  
Spread  
CLK1  
CLK2  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
STROBE  
Spectrum  
SCLK  
DATA  
Divide  
Logic  
and  
Output  
Enable  
Control  
PLL2  
PLL3  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
X2  
GND  
2
External capacitors are  
required with a crystal input.  
PDTS  
IDT® SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH  
1
ICS309  
REV L 091311  

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