Datasheet > 301A

301A

更新时间： 2024-10-30 07:45:35

品牌	Logo	应用领域
矽成 - ICSI		复用器
页数	文件大小	规格书
19页	299K
描述
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER

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中文翻译

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301A 数据手册

ICS85301

2:1

DIFFERENTIAL-TO-LVPECL MULTIPLEXER

Integrated

Circuit

Systems, Inc.

GENERAL DESCRIPTION

FEATURES

The ICS85301 is a high performance 2:1 Differ- • 2:1 LVPECL MUX

ICS

HiPerClockS™

ential-to-LVPECL Multiplexer and a member of the

• One LVPECL output

HiPerClockS™family of High Performance Clock

Solutions from ICS.The ICS85301 can also per-

form differential translation because the differ-

• Two differential clock inputs can accept: LVPECL, LVDS,

CML

ential inputs accept LVPECL, CML as well as LVDS levels.

The ICS85301 is packaged in a small 3mm x 3mm

16 VFQFN package, making it ideal for use on space con-

strained boards.

• Maximum input/output frequency: 3GHz

• Translates LVCMOS/LVTTL input signals to LVPECL levels

by using a resistor bias network on nPCLK0, nPCLK0

• Propagation delay: 490ps (maximum)

• Part-to-part skew: 150ps (maximum)

• Additive phase jitter, RMS: 0.009ps (typical)

• Full 3.3V or 2.5V operating supply

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

PCLK0

nPCLK0

16 15 14 13

PCLK0

V^EE

nPCLK0

PCLK1

nPCLK1

PCLK1

10 nQ

V^EE

nPCLK1

CLK_SEL

V_BB

ICS85301

16-Lead VFQFN

3mm x 3mm x 0.95 package body

K Package

TopView

PCLK0

nPCLK0

PCLK1

nPCLK1

V^BB

V^EE

VEE

VCC

VEE

CLK_SEL

V^EE

V^CC

ICS85301

16-LeadTSSOP

4.4mm x 5.0mm x 0.92mm

package body

G Package

TopView

85301AK

www.icst.com/products/hiperclocks.html

REV.A JANUARY 16, 2006

12 3 4 5 6 7...19

中文翻译

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