2N3955
MONOLITHIC DUAL
N-CHANNEL JFET
The 2N3955 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
FEATURES
LOW DRIFT
LOW LEAKAGE
LOW NOISE
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
The 2N3955 family are matched JFET pairs for
differential amplifiers. The 2N3955 family of general
purpose JFETs is characterized for low and medium
frequency differential amplifiers requiring low offset
voltage, drift, noise and capacitance
|∆ VGS1‐2 /∆T|= 5µV/°C max.
IG = 20pA TYP.
en = 10nV/√Hz TYP.
The 2N3955 family exhibits low capacitance - 6pF max
and a spot noise figure of - 0.5dB max. The part offers
a superior tracking ability.
Maximum Temperatures
Storage Temperature
‐65°C to +200°C
Operating Junction Temperature
Maximum Voltage and Current for Each Transistor – Note 1
+150°C
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
‐VGSS
‐VDSO
‐IG(f)
Gate Voltage to Drain or Source
Drain to Source Voltage
Gate Forward Current
60V
60V
50mA
(See Packaging Information).
Maximum Power Dissipation
Device Dissipation @ Free Air – Total
400mW @ 25°C
2N3955 Applications:
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
| V GS1‐2 / T| max.
CHARACTERISTICS VALUE UNITS CONDITIONS
Wideband Differential Amps
High Input Impedance Amplifiers
DRIFT VS.
25
µV/°C
VDG=20V, ID=200µA
TA=‐55°C to +125°C
VDG=20V, ID=200µA
TEMPERATURE
| V GS1‐2 | max.
OFFSET VOLTAGE
10
mV
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
BVGSS
BVGGO
CHARACTERISTICS
Breakdown Voltage
Gate‐To‐Gate Breakdown
TRANSCONDUCTANCE
Full Conduction
MIN.
60
60
TYP.
‐‐
‐‐
MAX.
‐‐
‐‐
UNITS
V
V
CONDITIONS
VDS = 0
I G= 1nA
ID=1µA
ID= 0
IS= 0
YfSS
YfS
|YFS1‐2 / Y FS|
1000
500
‐‐
2000
700
0.6
3000
1000
3
µmho
µmho
%
VDG= 20V
VDG= 20V
VGS= 0V f = 1kHz
ID= 200µA
Typical Operation
Mismatch
DRAIN CURRENT
Full Conduction
IDSS
|IDSS1‐2 / IDSS
0.5
‐‐
2
1
5
5
mA
%
VDG= 20V
VGS= 0V
|
Mismatch at Full Conduction
Click To Buy
GATE VOLTAGE
VGS(off) or Vp
VGS(on)
Pinchoff voltage
Operating Range
GATE CURRENT
Operating
1
0.5
2
‐‐
4.5
4
V
V
VDS= 20V
VDS=20V
ID= 1nA
ID=200µA
‐IG
‐IG
‐IG
‐‐
‐‐
‐‐
‐‐
20
‐‐
5
50
50
‐‐
pA
nA
pA
pA
VDG= 20V
TA= +125°C
ID= 200µA
High Temperature
Reduced VDG
VDG= 10V
VDG= 20V
ID= 200µA
VDS= 0
‐IGSS
At Full Conduction
OUTPUT CONDUCTANCE
Full Conduction
Operating
‐‐
100
YOSS
YOS
|YOS1‐2
‐‐
‐‐
‐‐
‐‐
0.1
0.01
5
1
0.1
µmho
µmho
µmho
VDG= 20V
VDG= 20V
VGS= 0V
ID= 200µA
|
Differential
COMMON MODE REJECTION
‐20 log | VGS1‐2/ VDS|
‐20 log | VGS1‐2/ VDS|
NOISE
CMR
CMR
‐‐
‐‐
100
75
‐‐
‐‐
dB
dB
∆VDS = 10 to 20V
∆VDS = 5 to 10V
VDS= 20V VGS= 0V
f= 100Hz NBW= 6Hz
VDS=20V ID=200µA f=10Hz NBW=1Hz
ID=200µA
ID=200µA
RG= 10MΩ
NF
en
Figure
Voltage
‐‐
‐‐
‐‐
‐‐
0.5
15
dB
nV/√Hz
CAPACITANCE
Input
Reverse Transfer
Drain‐to‐Drain
CISS
CRSS
CDD
‐‐
‐‐
‐‐
‐‐
‐‐
0.1
6
2
‐‐
pF
pF
pF
VDS= 20V
VGS= 0V
f= 1MHz
VDG= 20V
ID= 200µA
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP / SOIC (Top View)
Micross Components Europe
Available Packages:
2N3955 in PDIP / SOIC
2N3955 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
5秒后页面跳转
全球首块英伟达H200交付 黄仁勋“送货上门”
常用8脚开关电源芯片型号大全
74HC04芯片引脚图及功能、应用电路图讲解
CR6842芯片参数、引脚配置、应用电路图详解
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
