Datasheet > 2CW032300JL

2CW032300JL

更新时间： 2024-11-14 06:17:47

品牌	Logo	应用领域
士兰微 - SILAN		二极管齐纳二极管
页数	文件大小	规格书
3页	103K
描述
2CW032XXXJL SERIES ZENER DIODE CHIPS FOR PLASTIC PACKAGE

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

2CW032300JL 数据手册

2CW032XXXJL SERIES ZENER DIODE CHIPS FOR PLASTIC PACKAGE

DESCRIPTION

2CW032XXXJL series are low-power zener diode chips for

plastic package that fabricated in silicon epitaxial planar

technology.

The series can provide two precisions voltage chips

different regulator voltage.

The chip thickness is 180μm or 150μm. The top electrode

material is Al, and the back-side electrode material is Au.

Chip size: 0.32 X 0.32 (mm)².

Pad Size: 0.18 X 0.18 (mm)².

2CW032XXXJL CHIP TOPOGRAPHY

Ordering Specification

Seriies

Specification

2% tolerance

5% tolerance

2CW032XXXJL-2

2CW032XXXJL

ABSOLUTE MAXIMUM RATINGS

Characteristics

Junction Temperature

Storage Temperature

Symbol

Test conditions

Value

175

Unit

°C

----

-50~+175

°C

stg

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

Http: www.silan.com.cn

REV:1.0

2008.05.05

Page 1 of 3

12 3

中文翻译

下载PDF

与2CW032300JL相关器件

型号	品牌	获取价格	描述	数据表
2CW032300JL-R	SILAN	获取价格	2CW032XXXJL-R SERIES ZENER DIODE CHIPS FOR PLASTIC PACKAGE WITH ASYMMETRY LIMITS
2CW032300YQ	SILAN	获取价格	2CW032XXXYQ SERIES ZENER DIODE CHIPS FOR GLASS SEAL
2CW032300YQ-2	SILAN	获取价格	2CW032XXXYQ SERIES ZENER DIODE CHIPS FOR GLASS SEAL
2CW032300YQ-5	SILAN	获取价格	2CW032XXXYQ SERIES ZENER DIODE CHIPS FOR GLASS SEAL
2CW032300YQ-PA	SILAN	获取价格	2CW032XXXYQ-PX SERIES ZENER DIODE CHIPS FOR GLASS SEAL WITH ASYMMETRY LIMITS
2CW032300YQ-PB	SILAN	获取价格	2CW032XXXYQ-PX SERIES ZENER DIODE CHIPS FOR GLASS SEAL WITH ASYMMETRY LIMITS
2CW032300YQ-PC	SILAN	获取价格	2CW032XXXYQ-PX SERIES ZENER DIODE CHIPS FOR GLASS SEAL WITH ASYMMETRY LIMITS
2CW032300YQ-PD	SILAN	获取价格	2CW032XXXYQ-PX SERIES ZENER DIODE CHIPS FOR GLASS SEAL WITH ASYMMETRY LIMITS
2CW032330JL	SILAN	获取价格	2CW032XXXJL SERIES ZENER DIODE CHIPS FOR PLASTIC PACKAGE
2CW032330JL-R	SILAN	获取价格	2CW032XXXJL-R SERIES ZENER DIODE CHIPS FOR PLASTIC PACKAGE WITH ASYMMETRY LIMITS