Datasheet > 29306-BRF-001-A

29306-BRF-001-A

更新时间： 2024-11-08 01:19:59

品牌	Logo	应用领域
泰科 - TE		/
页数	文件大小	规格书
2页	511K
描述
6-Port DS3/E3/STS-1 Integrated Line Termination

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29306-BRF-001-A 数据手册

6-Port DS3/E3/STS-1 Integrated Line Termination

Device for ATM, Packet Processing and TDM Transport

M29306–DS3/E3/STS-1 “Line-Card-on-a-Chip”

The M29306 provides the most complete physical-layer

KEY FEATURES

solution for flexible DS3/E3/STS-1 ATM, packet and TDM

services on a single chip. The M29306 aggressively drives

down cost for existing solutions and as well as reduces

PCB real-estate and power.

> High integration – LIUs

with DJAT, T3/E3, STS-1

framers/mappers,

STS-12/STM-4 framer,

ATM & HDLC processors

> ATM/packet interfaces

– SPI-3, 8-bit 25–104 MHz

– UTOPIA Level 2/POS-PHY

Level 2, 16-bit 25-50 MHz

> Flexibility – mix ATM, TDM and > Fractional T3/E3 support

Each port of the M29306 operates independently allowing

for a mix of different rates and protocols. This flexibility

allows service providers to provide a combination of clear

channel DS3/E3 for packet, DS3/E3 ATM UNI or T3/E3/STS-1

TDM services on the same card. This enables ADMs/OEDs

and MSPPs to deploy a single line card that supports the

simultaneous mapping for SDH or SONET transport of both

DS3 and E3.

packet as well as T3, E3 and

> T3/E3/STS-1 payload

STS-1 services on one device

access

> Easy implementation –TAP

> Embedded CLADs for

software + high integration

supported line rates

= faster time-to-market

> Pattern generator/detector

> Parallel 8-bit, 77.76 MHz TDM

for BERT

telecom bus

> Comprehensive loopbacks

The M29306 integrates all the functional physical-layer

blocks for a DS3/E3/STS-1 line card. It includes: 6 inde-

pendent electrical line interface units (LIUs) with built-in

digital jitter attenuators (DJAT), 12 DS3/E3 framers, and 6

STS-1 framers. Each port is supported by a number of

protocol options that may be selected on a per port basis

from high level data link controllers (HDLC), ATM cell

delineators, or DS3/E3 SONET/SDH mappers/demappers.

The only requirement on the line side is the addition of

transformers and passive termination.

The M29306 requires only one 19.44 MHz reference clock

(passive crystal) for generating all the necessary internal

line rate clocks and enabling the same reference clock to

be available on an output pad. In addition it can use a 77.76

MHz or 155.52 MHz reference.

Fractional DS3/E3 service is also supported through a

bypass mode that allows external access to the DS3/E3

channel’s data stream between the framer and the

ATM/HDLC control allowing for external processing of

the payload. This bypass mode also provides the capability

of chaining two M29306s together to support a 12 line to

one system side implementation. A STS-1 bypass on each

of the STS-1 framers also allows for external access to

the STS-1 payload.

The device incorporates flexible system interfaces to

support cell/packet termination into an industry-standard

system bus of UTOPIA Level 2 (UL2) for ATM, POS-PHY Level

2 or SPI-3 for HDLC packets, and STS-12/STM-4 support

for the SONET/SDH traffic via a standard 8-bit, 77 MHz TDM

telecom bus. Thus, a channelized OC-12/STM-4 can be broken

down to DS3/E3 streams by the M29306 on a channel-by-

channel basis.

中文翻译

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与29306-BRF-001-A相关器件

型号	品牌	获取价格	描述	数据表
29306-BRF-001-A_15	TE	获取价格	6-Port DS3/E3/STS-1 Integrated Line Termination Device for ATM
293100B472JO0	CDE	获取价格	293100B472JO0
293100B502GO0	CDE	获取价格	Mica Capacitor, Mica
293100B502JO0	CDE	获取价格	293100B502JO0
293100B512JO0	CDE	获取价格	293100B512JO0
293100B562GO0	CDE	获取价格	Mica Capacitor, Mica
293100B562GO2	CDE	获取价格	Mica Capacitor, Mica, 10000V, 2% +Tol, 2% -Tol, 0.0056uF,
293100B562JO0	CDE	获取价格	293100B562JO0
293100B602JO0	CDE	获取价格	293100B602JO0
293100B622GO1	CDE	获取价格	Mica Capacitor, Mica, 10000V, 2% +Tol, 2% -Tol, 0.0062uF,

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