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28C04AFTI/P

更新时间: 2024-11-20 03:55:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
10页 127K
描述
4K (512 x 8) CMOS EEPROM

28C04AFTI/P 数据手册

 浏览型号28C04AFTI/P的Datasheet PDF文件第2页浏览型号28C04AFTI/P的Datasheet PDF文件第3页浏览型号28C04AFTI/P的Datasheet PDF文件第4页浏览型号28C04AFTI/P的Datasheet PDF文件第5页浏览型号28C04AFTI/P的Datasheet PDF文件第6页浏览型号28C04AFTI/P的Datasheet PDF文件第7页 
Obsolete Device  
28C04A  
4K (512 x 8) CMOS EEPROM  
FEATURES  
PACKAGE TYPES  
• Fast Read Access Time—150 ns  
• CMOS Technology for Low Power Dissipation  
- 30 mA Active  
DIP  
A7  
A6  
• 1  
2
24 Vcc  
23 A8  
A5  
3
22 NC  
21 WE  
20 OE  
19 NC  
18 CE  
17 I/O7  
16 I/O6  
15 I/O5  
14 I/O4  
13 I/O3  
A4  
4
A3  
5
- 100 µA Standby  
A2  
6
• Fast Byte Write Time—200 µs or 1 ms  
• Data Retention >200 years  
• Endurance - Minimum 104 Erase/Write Cycles  
- Automatic Write Operation  
- Internal Control Timer  
A1  
7
A0  
8
I/O0  
I/O1  
I/O2  
9
10  
11  
VSS 12  
- Auto-Clear Before Write Operation  
- On-Chip Address and Data Latches  
• Data Polling  
PLCC  
• Chip Clear Operation  
A6  
5
6
7
8
9
29 A8  
A5  
A4  
A3  
A2  
A1 10  
A0 11  
28 NC  
27 NC  
26 NC  
25 OE  
24 NC  
23 CE  
22 I/O7  
21 I/O6  
• Enhanced Data Protection  
- VCC Detector  
- Pulse Filter  
- Write Inhibit  
NC 12  
I/O0 13  
• 5-Volt-Only Operation  
• Organized 512x8 JEDEC standard pinout  
- 24-pin Dual-In-Line Package  
- 32-pin PLCC Package  
Pin 1 indicator on PLCC on top of package  
• Available for Extended Temperature Ranges:  
- Commercial: 0°C to +70°C  
- Industrial: -40°C to +85°C  
BLOCK DIAGRAM  
I/O0  
I/O7  
DESCRIPTION  
VSS  
Data Protection  
The Microchip Technology Inc. 28C04A is a CMOS 4K  
non-volatile electrically Erasable and Programmable  
Read Only Memory (EEPROM). The 28C04A is  
accessed like a static RAM for the read or write cycles  
without the need of external components. During a  
“byte write”, the address and data are latched inter-  
nally, freeing the microprocessor address and data bus  
for other operations. Following the initiation of write  
cycle, the device will go to a busy state and automati-  
cally clear and write the latched data using an internal  
control timer. To determine when a write cycle is com-  
plete, the 28C04A uses Data polling. Data polling  
allows the user to read the location last written to when  
the write operation is complete. CMOS design and pro-  
cessing enables this part to be used in systems where  
reduced power consumption and reliability are  
required. A complete family of packages is offered to  
provide the utmost flexibility in applications.  
VCC  
Circuitry  
Chip Enable/  
Output Enable  
Control Logic  
CE  
OE  
Input/Output  
Buffers  
WE  
Auto Erase/Write  
Timing  
Data  
Poll  
Program Voltage  
Generation  
A0  
Y
Y Gating  
Decoder  
L
a
t
c
h
e
s
4K bit  
Cell Matrix  
X
Decoder  
A8  
2004 Microchip Technology Inc.  
DS11126H-page 1  

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