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27C17A-20P PDF预览

27C17A-20P

更新时间: 2024-11-06 22:44:59
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
8页 70K
描述
16K (2K x 8) CMOS EEPROM

27C17A-20P 数据手册

 浏览型号27C17A-20P的Datasheet PDF文件第2页浏览型号27C17A-20P的Datasheet PDF文件第3页浏览型号27C17A-20P的Datasheet PDF文件第4页浏览型号27C17A-20P的Datasheet PDF文件第5页浏览型号27C17A-20P的Datasheet PDF文件第6页浏览型号27C17A-20P的Datasheet PDF文件第7页 
28C17A  
16K (2K x 8) CMOS EEPROM  
PACKAGE TYPES  
FEATURES  
RDY/BSY  
NC  
• 1  
2
28 Vcc  
27 WE  
26 NC  
25 A8  
• Fast Read Access Time—150 ns  
• CMOS Technology for Low Power Dissipation  
- 30 mA Active  
A7  
3
A6  
4
A6  
A5  
A4  
A3  
A2  
A1 10  
A0 11  
NC 12  
I/O0 13  
5
6
7
8
9
29 A8  
28 A9  
A5  
5
24 A9  
- 100 µA Standby  
A4  
6
23 NC  
22 OE  
21 A10  
20 CE  
19 I/O7  
18 I/O6  
17 I/O5  
16 I/O4  
15 I/O3  
27 NC  
26 NC  
25 OE  
24 A10  
23 CE  
22 I/O7  
21 I/O6  
• Fast Byte Write Time—200 µs or 1 ms  
• Data Retention >200 years  
A3  
7
A2  
8
A1  
9
4
• High Endurance - Minimum 10 Erase/Write Cycles  
A0  
10  
11  
12  
13  
I/O0  
I/O1  
I/O2  
• Automatic Write Operation  
- Internal Control Timer  
- Auto-Clear Before Write Operation  
- On-Chip Address and Data Latches  
• Data Polling; Ready/Busy  
• Chip Clear Operation  
• Enhanced Data Protection  
- VCC Detector  
- Pulse Filter  
VSS 14  
• Pin 1 indicator on PLCC on top of package  
OE  
NC  
A9  
1
2
3
4
5
6
7
28 A10  
27 CE  
26 I/07  
25 I/06  
24 I/05  
23 I/04  
22 I/03  
A8  
NC  
WE  
Vcc  
- Write Inhibit  
• Electronic Signature for Device Identification  
• 5-Volt-Only Operation  
• Organized 2Kx8 JEDEC Standard Pinout  
- 28 Pin Dual-In-Line Package  
- 32-Pin PLCC Package  
- 28-Pin Thin Small Outline Package (TSOP)  
8x20mm  
- 28-Pin Very Small Outline Package (VSOP)  
8x13.4mm  
• Available for Extended Temperature Ranges:  
- Commercial: 0˚C to +70˚C  
- Industrial: -40˚C to +85˚C  
RDY/BSY  
NC  
8
9
21 Vss  
20 I/02  
19 I/01  
18 I/00  
17 A0  
16 A1  
15 A2  
A7 10  
A6 11  
A5 12  
A4 13  
A3 14  
OE  
NC  
A9  
A8  
NC  
WE  
22  
23  
24  
25  
26  
27  
A10  
CE  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
VSS  
I/O2  
I/O1  
I/O0  
A0  
28  
1
VCC  
RDY/BSY  
2
3
4
5
6
7
NC  
A7  
A6  
A5  
A4  
A3  
A1  
A2  
8
DESCRIPTION  
BLOCK DIAGRAM  
The Microchip Technology Inc. 28C17A is a CMOS 16K non-  
volatile electrically Erasable PROM. The 28C17A is  
accessed like a static RAM for the read or write cycles without  
the need of external components. During a “byte write”, the  
address and data are latched internally, freeing the micropro-  
cessor address and data bus for other operations. Following  
the initiation of write cycle, the device will go to a busy state  
and automatically clear and write the latched data using an  
internal control timer. To determine when the write cycle is  
complete, the user has a choice of monitoring the Ready/  
Busy output or using Data polling. The Ready/Busy pin is an  
open drain output, which allows easy configuration in wired-  
or systems. Alternatively, Data polling allows the user to read  
the location last written to when the write operation is com-  
plete. CMOS design and processing enables this part to be  
used in systems where reduced power consumption and reli-  
ability are required. A complete family of packages is offered  
to provide the utmost flexibility in applications.  
I/O0  
I/O7  
VSS  
Data Protection  
VCC  
Circuitry  
Chip Enable/  
Output Enable  
Control Logic  
CE  
OE  
WE  
Input/Output  
Buffers  
Auto Erase/Write  
Timing  
Data  
Poll  
Rdy/  
Busy  
Program Voltage  
Generation  
A0  
Y
Y Gating  
Decoder  
L
a
t
c
h
e
s
16K bit  
X
Decoder  
Cell Matrix  
A10  
1996 Microchip Technology Inc.  
DS11127G-page 1  
This document was created with FrameMaker 4 0 4  

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