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256KX18 PDF预览

256KX18

更新时间: 2024-11-26 06:24:11
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
29页 445K
描述
128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

256KX18 数据手册

 浏览型号256KX18的Datasheet PDF文件第2页浏览型号256KX18的Datasheet PDF文件第3页浏览型号256KX18的Datasheet PDF文件第4页浏览型号256KX18的Datasheet PDF文件第5页浏览型号256KX18的Datasheet PDF文件第6页浏览型号256KX18的Datasheet PDF文件第7页 
                                                              
                                                             
IS61NLP12832B  
IS61NLP12836B/IS61NVP12836B  
IS61NLP25618A/IS61NVP25618A  
128K x 32, 128K x 36, and 256K x 18  
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
SEPTEMBER 2007  
FEATURES  
DESCRIPTION  
Theꢀ4ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingandcommunicationsapplications.Theyareꢀ  
organizedꢀasꢀ128Kꢀwordsꢀbyꢀ32ꢀbits,ꢀ128Kꢀwordsꢀbyꢀ36ꢀ  
bits,ꢀandꢀ256Kꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ  
advanced CMOS technology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminated when the bus switches from read to write, or  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
into a single monolithic circuit.  
data and control  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ing MODE input  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operationsꢀ  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
device will hold their previous values.  
and address pipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKE pin to enable clock and suspend operation  
AllRead,WriteandDeselectcyclesareinitiatedbytheADVꢀ  
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ119-  
ballꢀPBGAꢀpackages  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isincremented.Newexternaladdressescanbeloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ Powerꢀsupply:  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
by the rising edge of the clock inputs and when WE is  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
NVP:ꢀVd d 2.5Vꢀ(±ꢀ5%),ꢀVd d q ꢀ2.5Vꢀ(±ꢀ5%)  
NLP:ꢀVd d ꢀ3.3Vꢀ(±ꢀ5%),ꢀVd d q ꢀ3.3V/2.5Vꢀ(±ꢀ5%)  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.WhentiedHIGH,theinterleavedburstsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FAST ACCESS TIME  
Symbol  
Parameter  
-250  
2.6ꢀ  
4ꢀ  
-200  
3.1ꢀ  
5ꢀ  
Units  
ns  
tk q ꢀ  
tk c ꢀ  
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
Frequencyꢀ  
250ꢀ  
200ꢀ  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. D  
09/10/07  

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