Datasheet > 24LC64TI-/SM

24LC64TI-/SM

更新时间： 2024-01-19 02:20:43

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数	文件大小	规格书
44页	1286K
描述
8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8

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24LC64TI-/SM 数据手册

24AA64/24LC64/24FC64

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

4.0

BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically,

unlimited (although only the last thirty two will be stored

when doing a write operation). When an overwrite does

occur, it will replace data in a first-in first-out (FIFO)

fashion.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.5

Acknowledge

4.1

Bus Not Busy (A)

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

Note:

The 24XX64 does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an Acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24XX64) will leave the data line

high to enable the master to generate the Stop

condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

SCL

SDA

Start

Condition

Stop

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

DS21189S-page 6

 1997-2012 Microchip Technology Inc.

1...3 4 567 8 9...44

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与24LC64TI-/SM相关器件

型号	品牌	描述	获取价格	数据表
24LC64T-I/SMG	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24LC64T-I/SMRVA	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24LC64TI/SN	MICROCHIP	暂无描述	获取价格
24LC64T-I/SN	MICROCHIP	64K I2C⑩ Serial EEPROM	获取价格
24LC64TI-/SN	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	获取价格
24LC64T-I/SN101	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8	获取价格

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