Datasheet > 24LC64TI-/SM

24LC64TI-/SM

更新时间： 2023-01-03 02:03:50

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数	文件大小	规格书
44页	1286K
描述
8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8

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数据手册

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24LC64TI-/SM 数据手册

24AA64/24LC64/24FC64

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24XX64 will select a read or

write operation.

5.0

DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a four-bit control code. For

the 24XX64, this is set as ‘1010’ binary for read and

write operations. The next three bits of the control byte

are the Chip Select bits (A2, A1, A0). The Chip Select

bits allow the use of up to eight 24XX64 devices on the

same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are, in effect, the three Most Significant bits of the word

address.

FIGURE 5-1:

CONTROL BYTE FORMAT

Read/Write Bit

Chip Select

Control Code

Bits

A2 A1 A0 R/W ACK

Slave Address

Acknowledge Bit

Start Bit

For the SOT-23 and Chip Scale packages, the address

pins are not available. During device addressing, the

A2, A1 and A0 Chip Select bits (Figure 5-2) should be

set to ‘0’.

5.1

Contiguous Addressing Across

Multiple Devices

The last bit of the control byte defines the operation to

be performed. When set to a ‘1’, a read operation is

selected. When set to a ‘0’, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A12...A0 are used, the upper-three address bits

are “don’t care” bits. The upper-address bits are

transferred first, followed by the Less Significant bits.

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 512K

bits by adding up to eight 24XX64 devices on the same

bus. In this case, software can use A0 of the control

byte as address bit A13; A1 as address bit A14; and A2

as address bit A15. It is not possible to sequentially

read across device boundaries.

Following the Start condition, the 24XX64 monitors the

SDA bus, checking the device-type identifier being

transmitted. Upon receiving a ‘1010’ code and appro-

priate device-select bits, the slave device outputs an

The SOT-23 and Chip Scale packages do not support

multiple device addressing on the same bus.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte

Address High Byte

Address Low Byte

•

R/W

12 11

Control

Code

Chip

Select

bits

x= “don’t care” bit

 1997-2012 Microchip Technology Inc.

DS21189S-page 7

1...4 5 678 9 10...44

中文翻译

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与24LC64TI-/SM相关器件

型号	品牌	获取价格	描述	数据表
24LC64T-I/SMG	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8
24LC64T-I/SMRVA	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8
24LC64TI/SN	MICROCHIP	获取价格	暂无描述
24LC64T-I/SN	MICROCHIP	获取价格	64K I2C⑩ Serial EEPROM
24LC64TI-/SN	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8
24LC64T-I/SN101	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8
24LC64TI/SNG	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.150 INCH, LEAD FREE, PLASTIC, MS-012, SOIC-8
24LC64T-I/SNG	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8
24LC64T-I/SNVAO	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 3.90 MM, ROHS COMPLIANT, PLASTIC, SOIC-8
24LC64TI/ST	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8

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