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24LC64-I/SMG

更新时间： 2024-02-15 09:19:44
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
12页 184K
描述
8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8

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24LC64-I/SMG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51Factory Lead Time：6 weeks
风险等级：1.02Is Samacsys：N
其他特性：DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED最大时钟频率 (fCLK)：0.4 MHz
数据保留时间-最小值：200耐久性：1000000 Write/Erase Cycles
I2C控制字节：1010DDDRJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.4 mm
内存密度：65536 bit内存集成电路类型：EEPROM
内存宽度：8湿度敏感等级：1
功能数量：1端子数量：8
字数：8192 words字数代码：8000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：8KX8
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：260电源：2/5 V
认证状态：Not Qualified座面最大高度：1.1 mm
串行总线类型：I2C最大待机电流：0.000001 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3 mm
最长写入周期时间 (tWC)：5 ms写保护：HARDWARE
Base Number Matches：1

24LC64-I/SMG 数据手册

 浏览型号24LC64-I/SMG的Datasheet PDF文件第6页浏览型号24LC64-I/SMG的Datasheet PDF文件第7页浏览型号24LC64-I/SMG的Datasheet PDF文件第8页浏览型号24LC64-I/SMG的Datasheet PDF文件第10页浏览型号24LC64-I/SMG的Datasheet PDF文件第11页浏览型号24LC64-I/SMG的Datasheet PDF文件第12页 
24AA64/24LC64  
8.2  
Random Read  
8.0  
READ OPERATION  
Read operations are initiated in the same way as write  
operations with the exception that the R/W bit of the  
control byte is set to one. There are three basic types  
of read operations: current address read, random read,  
and sequential read.  
Random read operations allow the master to access  
any memory location in a random manner. To perform  
this type of read operation, first the word address must  
be set.This is done by sending the word address to the  
24xx64 as part of a write operation (R/W bit set to 0).  
After the word address is sent, the master generates a  
start condition following the acknowledge. This termi-  
nates the write operation, but not before the internal  
address pointer is set. Then the master issues the  
control byte again but with the R/W bit set to a one.The  
24xx64 will then issue an acknowledge and transmit  
the 8-bit data word. The master will not acknowledge  
the transfer but does generate a stop condition which  
causes the 24xx64 to discontinue transmission  
(Figure 8-2). After a random read command, the inter-  
nal address counter will point to the address location  
following the one that was just read.  
8.1  
Current Address Read  
The 24xx64 contains an address counter that main-  
tains the address of the last word accessed, internally  
incremented by one. Therefore, if the previous read  
access was to address n (n is any legal address), the  
next current address read operation would access data  
from address n + 1.  
Upon receipt of the control byte with R/W bit set to one,  
the 24xx64 issues an acknowledge and transmits the  
eight bit data word. The master will not acknowledge  
the transfer but does generate a stop condition and the  
24xx64 discontinues transmission (Figure 8-1).  
8.3  
Sequential Read  
Sequential reads are initiated in the same way as a ran-  
dom read except that after the 24xx64 transmits the  
first data byte, the master issues an acknowledge as  
opposed to the stop condition used in a random read.  
This acknowledge directs the 24xx64 to transmit the  
next sequentially addressed 8-bit word (Figure 8-3).  
Following the final byte transmitted to the master, the  
master will NOT generate an acknowledge but will gen-  
erate a stop condition. To provide sequential reads the  
24xx64 contains an internal address pointer which is  
incremented by one at the completion of each opera-  
tion. This address pointer allows the entire memory  
contents to be serially read during one operation. The  
internal address pointer will automatically roll over from  
address 1FFF to address 0000 if the master acknowl-  
edges the byte received from the array address 1FFF.  
FIGURE 8-1: CURRENT ADDRESS READ  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY  
MASTER  
CONTROL  
BYTE  
DATA  
BYTE  
A A A  
2 1 0  
SDA LINE  
S 1 0 1 0  
1
P
A
C
K
N
O
BUS ACTIVITY  
A
C
K
FIGURE 8-2: RANDOM READ  
S
S
BUS ACTIVITY  
MASTER  
T
A
R
T
T
A
R
T
S
T
O
P
CONTROL  
BYTE  
ADDRESS  
HIGH BYTE  
ADDRESS  
LOW BYTE  
CONTROL  
BYTE  
DATA  
BYTE  
A A A  
2 1 0  
A A A  
2 1 0  
SDA LINE  
X X X  
S 1 0 1 0  
0
S 1 0 1 0  
1
P
A
C
K
A
C
K
A
C
K
N
O
A
C
A
C
K
BUS ACTIVITY  
X = Don’t Care Bit  
FIGURE 8-3: SEQUENTIAL READ  
S
BUS ACTIVITY  
CONTROL  
T
DATA n  
DATA n + 1  
DATA n + 2  
DATA n + X  
MASTER  
SDA LINE  
O
P
BYTE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY  
A
C
K
1998 Microchip Technology Inc.  
DS21189B-page 9  
 
 
 
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